Merge branch 'master' into stabilize-aarch64-sha3-intrinsics

tarcieri · tarcieri · commit a8671e89ce06 · 2024-04-11T07:51:34.000-06:00
Also bumps nightly version to 1.79.0
diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -15,7 +15,7 @@ use stdarch_test::assert_instr;
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -31,7 +31,7 @@ pub unsafe fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -47,7 +47,7 @@ pub unsafe fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -63,7 +63,7 @@ pub unsafe fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -79,7 +79,7 @@ pub unsafe fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -95,7 +95,7 @@ pub unsafe fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -111,7 +111,7 @@ pub unsafe fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -127,7 +127,7 @@ pub unsafe fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(eor3))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -9977,7 +9977,7 @@ pub unsafe fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -9993,7 +9993,7 @@ pub unsafe fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -10009,7 +10009,7 @@ pub unsafe fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -10025,7 +10025,7 @@ pub unsafe fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -10041,7 +10041,7 @@ pub unsafe fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -10057,7 +10057,7 @@ pub unsafe fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -10073,7 +10073,7 @@ pub unsafe fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -10089,7 +10089,7 @@ pub unsafe fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(bcax))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -15261,7 +15261,7 @@ pub unsafe fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(rax1))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -15277,7 +15277,7 @@ pub unsafe fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -15293,7 +15293,7 @@ pub unsafe fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h2))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -15309,7 +15309,7 @@ pub unsafe fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uin
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su0))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
@@ -15325,7 +15325,7 @@ pub unsafe fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su1))]
-#[stable(feature = "stdarch_neon_sha3", since = "1.78.0")]
+#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 pub unsafe fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
     #[allow(improper_ctypes)]
     extern "unadjusted" {
diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs
@@ -28363,8 +28363,7 @@ pub unsafe fn _mm_maskz_set1_epi64(k: __mmask8, a: i64) -> __m128i {
 #[target_feature(enable = "avx512f")]
 #[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
 pub unsafe fn _mm512_set4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
-    let r = i64x8::new(d, c, b, a, d, c, b, a);
-    transmute(r)
+    _mm512_set_epi64(d, c, b, a, d, c, b, a)
 }
 
 /// Set packed 64-bit integers in dst with the repeated 4 element sequence in reverse order.
@@ -28374,8 +28373,7 @@ pub unsafe fn _mm512_set4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
 #[target_feature(enable = "avx512f")]
 #[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
 pub unsafe fn _mm512_setr4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i {
-    let r = i64x8::new(a, b, c, d, a, b, c, d);
-    transmute(r)
+    _mm512_set_epi64(a, b, c, d, a, b, c, d)
 }
 
 /// Compare packed single-precision (32-bit) floating-point elements in a and b for less-than, and store the results in mask vector k.
@@ -34486,7 +34484,7 @@ pub unsafe fn _mm_maskz_expandloadu_ps(k: __mmask8, mem_addr: *const f32) -> __m
     dst
 }
 
-/// Load contiguous active single-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+/// Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_expandloadu_pd)
 #[inline]
@@ -34508,7 +34506,7 @@ pub unsafe fn _mm512_mask_expandloadu_pd(
     dst
 }
 
-/// Load contiguous active single-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+/// Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_expandloadu_pd)
 #[inline]
@@ -34526,7 +34524,7 @@ pub unsafe fn _mm512_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) ->
     dst
 }
 
-/// Load contiguous active single-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+/// Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_expandloadu_pd)
 #[inline]
@@ -34548,7 +34546,7 @@ pub unsafe fn _mm256_mask_expandloadu_pd(
     dst
 }
 
-/// Load contiguous active single-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+/// Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_expandloadu_pd)
 #[inline]
@@ -34566,7 +34564,7 @@ pub unsafe fn _mm256_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) ->
     dst
 }
 
-/// Load contiguous active single-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
+/// Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_expandloadu_pd)
 #[inline]
@@ -34584,7 +34582,7 @@ pub unsafe fn _mm_mask_expandloadu_pd(src: __m128d, k: __mmask8, mem_addr: *cons
     dst
 }
 
-/// Load contiguous active single-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
+/// Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at mem_addr (those with their respective bit set in mask k), and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
 ///
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_expandloadu_pd)
 #[inline]
diff --git a/crates/intrinsic-test/src/json_parser.rs b/crates/intrinsic-test/src/json_parser.rs
@@ -19,6 +19,7 @@ pub enum ArgPrep {
     Register {
         #[allow(dead_code)]
         #[serde(rename = "register")]
+        #[allow(dead_code)]
         reg: String,
     },
     Immediate {
diff --git a/crates/stdarch-gen-arm/src/main.rs b/crates/stdarch-gen-arm/src/main.rs
