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[clippy] fix clippy issues
1 parent 104a6b3 commit cb3b0a3

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10 files changed

+62
-51
lines changed

10 files changed

+62
-51
lines changed

‎src/lib.rs

+3-1
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
//! others at:
2727
//!
2828
//! * [i686](https://rust-lang-nursery.github.io/stdsimd/i686/stdsimd/)
29-
//! * [x86_64](https://rust-lang-nursery.github.io/stdsimd/x86_64/stdsimd/)
29+
//! * [`x86_64`](https://rust-lang-nursery.github.io/stdsimd/x86_64/stdsimd/)
3030
//! * [arm](https://rust-lang-nursery.github.io/stdsimd/arm/stdsimd/)
3131
//! * [aarch64](https://rust-lang-nursery.github.io/stdsimd/aarch64/stdsimd/)
3232
//!
@@ -117,6 +117,8 @@
117117
)]
118118
#![cfg_attr(test, feature(proc_macro, test))]
119119

120+
#![cfg_attr(feature = "cargo-clippy", allow(inline_always, too_many_arguments))]
121+
120122
#[cfg(test)]
121123
extern crate stdsimd_test;
122124

‎src/macros.rs

+11
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,8 @@ macro_rules! define_impl {
7777
}
7878

7979
#[inline(always)]
80+
#[cfg_attr(feature = "cargo-clippy", allow(cast_lossless,
81+
cast_precision_loss))]
8082
pub unsafe fn load_unchecked(
8183
slice: &[$elemty],
8284
offset: usize,
@@ -188,13 +190,21 @@ macro_rules! define_shifts {
188190
impl ::std::ops::Shl<$by> for $ty {
189191
type Output = Self;
190192
#[inline(always)]
193+
#[cfg_attr(feature = "cargo-clippy", allow(cast_lossless,
194+
cast_sign_loss,
195+
cast_possible_wrap,
196+
cast_possible_truncation))]
191197
fn shl(self, other: $by) -> Self {
192198
unsafe { simd_shl(self, $ty::splat(other as $elem)) }
193199
}
194200
}
195201
impl ::std::ops::Shr<$by> for $ty {
196202
type Output = Self;
197203
#[inline(always)]
204+
#[cfg_attr(feature = "cargo-clippy", allow(cast_lossless,
205+
cast_sign_loss,
206+
cast_possible_wrap,
207+
cast_possible_truncation))]
198208
fn shr(self, other: $by) -> Self {
199209
unsafe { simd_shr(self, $ty::splat(other as $elem)) }
200210
}
@@ -240,6 +250,7 @@ macro_rules! define_integer_ops {
240250
i8, i16, i32, i64, isize);
241251

242252
impl ::std::fmt::LowerHex for $ty {
253+
#[cfg_attr(feature = "cargo-clippy", allow(cast_possible_truncation))]
243254
fn fmt(&self, f: &mut ::std::fmt::Formatter) -> ::std::fmt::Result {
244255
write!(f, "{}(", stringify!($ty))?;
245256
let n = ::std::mem::size_of_val(self) / ::std::mem::size_of::<$elem>();

‎src/x86/avx.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -806,8 +806,8 @@ pub unsafe fn _mm_permutevar_ps(a: f32x4, b: i32x4) -> f32x4 {
806806
#[target_feature = "+avx"]
807807
#[cfg_attr(test, assert_instr(vpermilps, imm8 = 9))]
808808
pub unsafe fn _mm256_permute_ps(a: f32x8, imm8: i32) -> f32x8 {
809-
let imm8 = (imm8 & 0xFF) as u8;
810809
const fn add4(x: u32) -> u32 { x + 4 }
810+
let imm8 = (imm8 & 0xFF) as u8;
811811
macro_rules! shuffle4 {
812812
($a:expr, $b:expr, $c:expr, $d:expr) => {
813813
simd_shuffle8(a, _mm256_undefined_ps(), [

‎src/x86/avx2.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,7 @@ pub unsafe fn _mm256_adds_epu16(a: u16x16, b: u16x16) -> u16x16 {
100100
#[target_feature = "+avx2"]
101101
#[cfg_attr(test, assert_instr(vpalignr, n = 15))]
102102
pub unsafe fn _mm256_alignr_epi8(a: i8x32, b: i8x32, n: i32) -> i8x32 {
103+
const fn add(a: u32, b: u32) -> u32 { a + b }
103104
let n = n as u32;
104105
// If palignr is shifting the pair of vectors more than the size of two
105106
// lanes, emit zero.
@@ -114,7 +115,6 @@ pub unsafe fn _mm256_alignr_epi8(a: i8x32, b: i8x32, n: i32) -> i8x32 {
114115
(a, b, n)
115116
};
116117

117-
const fn add(a: u32, b: u32) -> u32 { a + b }
118118
macro_rules! shuffle {
119119
($shift:expr) => {
120120
simd_shuffle32(b, a, [

‎src/x86/bmi.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ use stdsimd_test::assert_instr;
1616
#[target_feature = "+bmi"]
1717
#[cfg_attr(test, assert_instr(bextr))]
1818
pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
19-
_bextr2_u32(a, (start & 0xffu32) | ((len & 0xffu32) << 8u32))
19+
_bextr2_u32(a, (start & 0xff_u32) | ((len & 0xff_u32) << 8_u32))
2020
}
2121

2222
/// Extracts bits in range [`start`, `start` + `length`) from `a` into
@@ -26,7 +26,7 @@ pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
2626
#[cfg_attr(test, assert_instr(bextr))]
2727
#[cfg(not(target_arch = "x86"))]
2828
pub unsafe fn _bextr_u64(a: u64, start: u64, len: u64) -> u64 {
29-
_bextr2_u64(a, (start & 0xffu64) | ((len & 0xffu64) << 8u64))
29+
_bextr2_u64(a, (start & 0xff_u64) | ((len & 0xff_u64) << 8_u64))
3030
}
3131

3232
/// Extracts bits of `a` specified by `control` into
@@ -92,7 +92,7 @@ pub unsafe fn _blsi_u64(x: u64) -> u64 {
9292
#[target_feature = "+bmi"]
9393
#[cfg_attr(test, assert_instr(blsmsk))]
9494
pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
95-
x ^ (x.wrapping_sub(1u32))
95+
x ^ (x.wrapping_sub(1_u32))
9696
}
9797

9898
/// Get mask up to lowest set bit.
@@ -101,7 +101,7 @@ pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
101101
#[cfg_attr(test, assert_instr(blsmsk))]
102102
#[cfg(not(target_arch = "x86"))] // generates lots of instructions
103103
pub unsafe fn _blsmsk_u64(x: u64) -> u64 {
104-
x ^ (x.wrapping_sub(1u64))
104+
x ^ (x.wrapping_sub(1_u64))
105105
}
106106

107107
/// Resets the lowest set bit of `x`.

‎src/x86/runtime.rs

+20-22
Original file line numberDiff line numberDiff line change
@@ -85,21 +85,18 @@ pub enum __Feature {
8585
__NonExhaustive
8686
}
8787

88+
/// Sets the `bit`-th bit of `x`.
8889
fn set_bit(x: usize, bit: u32) -> usize {
8990
debug_assert!(32 > bit);
9091
x | 1 << bit
9192
}
9293

94+
/// Tests the `bit`-th bit of `x`.
9395
fn test_bit(x: usize, bit: u32) -> bool {
9496
debug_assert!(32 > bit);
9597
x & (1 << bit) != 0
9698
}
9799

98-
fn inv_test_bit(v: usize, idx: u32) -> bool {
99-
debug_assert!(32 > idx);
100-
((v >> idx) & 1) != 0
101-
}
102-
103100
/// Run-time feature detection on x86 works by using the CPUID instruction.
104101
///
105102
/// The [CPUID Wikipedia page](https://en.wikipedia.org/wiki/CPUID) contains all
@@ -110,6 +107,7 @@ fn inv_test_bit(v: usize, idx: u32) -> bool {
110107
/// - [Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2: Instruction Set Reference, A-Z](http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf).
111108
/// - [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions](http://support.amd.com/TechDocs/24594.pdf).
112109
///
110+
#[cfg_attr(feature = "cargo-clippy", allow(similar_names))]
113111
fn detect_features() -> usize {
114112
let ebx;
115113
let ecx;
@@ -122,37 +120,37 @@ fn detect_features() -> usize {
122120
/// This gives us most of the CPU features in ECX and EDX (see below),
123121
asm!("cpuid"
124122
: "={ecx}"(ecx), "={edx}"(edx)
125-
: "{eax}"(0x00000001u32), "{ecx}"(0 as u32)
123+
: "{eax}"(0x0000_0001_u32), "{ecx}"(0 as u32)
126124
: :);
127125

128126
/// 2. EAX=7, ECX=0: Queries "Extended Features"
129127
/// This gives us information about bmi,bmi2, and avx2 support (see below).
130128
asm!("cpuid"
131129
: "={ebx}"(ebx)
132-
: "{eax}"(0x00000007u32), "{ecx}"(0 as u32)
130+
: "{eax}"(0x0000_0007_u32), "{ecx}"(0 as u32)
133131
: :);
134132
}
135133

136134
let mut value: usize = 0;
137135

138136
// CPUID call with EAX=7, ECX=0 => Extended Features in EBX and ECX (unneeded):
139-
if inv_test_bit(ebx, 3) { value = set_bit(value, __Feature::bmi as u32); }
140-
if inv_test_bit(ebx, 5) { value = set_bit(value, __Feature::avx2 as u32); }
141-
if inv_test_bit(ebx, 8) { value = set_bit(value, __Feature::bmi2 as u32); }
137+
if test_bit(ebx, 3) { value = set_bit(value, __Feature::bmi as u32); }
138+
if test_bit(ebx, 5) { value = set_bit(value, __Feature::avx2 as u32); }
139+
if test_bit(ebx, 8) { value = set_bit(value, __Feature::bmi2 as u32); }
142140

143141
// CPUID call with EAX=1 => feature bits in ECX and EDX:
144-
if inv_test_bit(ecx, 0) { value = set_bit(value, __Feature::sse3 as u32); }
145-
if inv_test_bit(ecx, 5) { value = set_bit(value, __Feature::abm as u32); }
146-
if inv_test_bit(ecx, 9) { value = set_bit(value, __Feature::ssse3 as u32); }
147-
if inv_test_bit(ecx, 12) { value = set_bit(value, __Feature::fma as u32); }
148-
if inv_test_bit(ecx, 19) { value = set_bit(value, __Feature::sse4_1 as u32); }
149-
if inv_test_bit(ecx, 20) { value = set_bit(value, __Feature::sse4_2 as u32); }
150-
if inv_test_bit(ecx, 21) { value = set_bit(value, __Feature::tbm as u32); }
151-
if inv_test_bit(ecx, 23) { value = set_bit(value, __Feature::popcnt as u32); }
152-
if inv_test_bit(ecx, 28) { value = set_bit(value, __Feature::avx as u32); }
153-
154-
if inv_test_bit(edx, 25) { value = set_bit(value, __Feature::sse as u32); }
155-
if inv_test_bit(edx, 26) { value = set_bit(value, __Feature::sse2 as u32); }
142+
if test_bit(ecx, 0) { value = set_bit(value, __Feature::sse3 as u32); }
143+
if test_bit(ecx, 5) { value = set_bit(value, __Feature::abm as u32); }
144+
if test_bit(ecx, 9) { value = set_bit(value, __Feature::ssse3 as u32); }
145+
if test_bit(ecx, 12) { value = set_bit(value, __Feature::fma as u32); }
146+
if test_bit(ecx, 19) { value = set_bit(value, __Feature::sse4_1 as u32); }
147+
if test_bit(ecx, 20) { value = set_bit(value, __Feature::sse4_2 as u32); }
148+
if test_bit(ecx, 21) { value = set_bit(value, __Feature::tbm as u32); }
149+
if test_bit(ecx, 23) { value = set_bit(value, __Feature::popcnt as u32); }
150+
if test_bit(ecx, 28) { value = set_bit(value, __Feature::avx as u32); }
151+
152+
if test_bit(edx, 25) { value = set_bit(value, __Feature::sse as u32); }
153+
if test_bit(edx, 26) { value = set_bit(value, __Feature::sse2 as u32); }
156154

157155
value
158156
}

‎src/x86/sse.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -561,7 +561,7 @@ pub unsafe fn _mm_sfence() {
561561
#[target_feature = "+sse"]
562562
#[cfg_attr(test, assert_instr(stmxcsr))]
563563
pub unsafe fn _mm_getcsr() -> u32 {
564-
let mut result = 0i32;
564+
let mut result = 0_i32;
565565
stmxcsr((&mut result) as *mut _ as *mut i8);
566566
result as u32
567567
}

‎src/x86/sse2.rs

+3-4
Original file line numberDiff line numberDiff line change
@@ -316,8 +316,8 @@ pub unsafe fn _mm_subs_epu16(a: u16x8, b: u16x8) -> u16x8 {
316316
#[target_feature = "+sse2"]
317317
#[cfg_attr(test, assert_instr(pslldq, imm8 = 1))]
318318
pub unsafe fn _mm_slli_si128(a: __m128i, imm8: i32) -> __m128i {
319-
let (zero, imm8) = (__m128i::splat(0), imm8 as u32);
320319
const fn sub(a: u32, b: u32) -> u32 { a - b }
320+
let (zero, imm8) = (__m128i::splat(0), imm8 as u32);
321321
macro_rules! shuffle {
322322
($shift:expr) => {
323323
simd_shuffle16::<__m128i, __m128i>(zero, a, [
@@ -453,8 +453,8 @@ pub unsafe fn _mm_sra_epi32(a: i32x4, count: i32x4) -> i32x4 {
453453
#[target_feature = "+sse2"]
454454
#[cfg_attr(test, assert_instr(psrldq, imm8 = 1))]
455455
pub unsafe fn _mm_srli_si128(a: __m128i, imm8: i32) -> __m128i {
456-
let (zero, imm8) = (__m128i::splat(0), imm8 as u32);
457456
const fn add(a: u32, b: u32) -> u32 { a + b }
457+
let (zero, imm8) = (__m128i::splat(0), imm8 as u32);
458458
macro_rules! shuffle {
459459
($shift:expr) => {
460460
simd_shuffle16::<__m128i, __m128i>(a, zero, [
@@ -1074,10 +1074,9 @@ pub unsafe fn _mm_shuffle_epi32(a: i32x4, imm8: i32) -> i32x4 {
10741074
#[target_feature = "+sse2"]
10751075
#[cfg_attr(test, assert_instr(pshufhw, imm8 = 9))]
10761076
pub unsafe fn _mm_shufflehi_epi16(a: i16x8, imm8: i32) -> i16x8 {
1077+
const fn add4(x: u32) -> u32 { x + 4 }
10771078
// See _mm_shuffle_epi32.
10781079
let imm8 = (imm8 & 0xFF) as u8;
1079-
const fn add4(x: u32) -> u32 { x + 4 }
1080-
10811080
macro_rules! shuffle_done {
10821081
($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
10831082
simd_shuffle8(a, a, [

‎src/x86/sse42.rs

+16-16
Original file line numberDiff line numberDiff line change
@@ -5,41 +5,41 @@ use v128::*;
55
use x86::__m128i;
66

77
/// String contains unsigned 8-bit characters *(Default)*
8-
pub const _SIDD_UBYTE_OPS: i8 = 0b00000000;
8+
pub const _SIDD_UBYTE_OPS: i8 = 0b0000_0000;
99
/// String contains unsigned 16-bit characters
10-
pub const _SIDD_UWORD_OPS: i8 = 0b00000001;
10+
pub const _SIDD_UWORD_OPS: i8 = 0b0000_0001;
1111
/// String contains signed 8-bit characters
12-
pub const _SIDD_SBYTE_OPS: i8 = 0b00000010;
12+
pub const _SIDD_SBYTE_OPS: i8 = 0b0000_0010;
1313
/// String contains unsigned 16-bit characters
14-
pub const _SIDD_SWORD_OPS: i8 = 0b00000011;
14+
pub const _SIDD_SWORD_OPS: i8 = 0b0000_0011;
1515

1616
/// For each character in `a`, find if it is in `b` *(Default)*
17-
pub const _SIDD_CMP_EQUAL_ANY: i8 = 0b00000000;
17+
pub const _SIDD_CMP_EQUAL_ANY: i8 = 0b0000_0000;
1818
/// For each character in `a`, determine if `b[0] <= c <= b[1] or b[1] <= c <= b[2]...`
19-
pub const _SIDD_CMP_RANGES: i8 = 0b00000100;
19+
pub const _SIDD_CMP_RANGES: i8 = 0b0000_0100;
2020
/// The strings defined by `a` and `b` are equal
21-
pub const _SIDD_CMP_EQUAL_EACH: i8 = 0b00001000;
21+
pub const _SIDD_CMP_EQUAL_EACH: i8 = 0b0000_1000;
2222
/// Search for the defined substring in the target
23-
pub const _SIDD_CMP_EQUAL_ORDERED: i8 = 0b00001100;
23+
pub const _SIDD_CMP_EQUAL_ORDERED: i8 = 0b0000_1100;
2424

2525
/// Do not negate results *(Default)*
26-
pub const _SIDD_POSITIVE_POLARITY: i8 = 0b00000000;
26+
pub const _SIDD_POSITIVE_POLARITY: i8 = 0b0000_0000;
2727
/// Negate results
28-
pub const _SIDD_NEGATIVE_POLARITY: i8 = 0b00010000;
28+
pub const _SIDD_NEGATIVE_POLARITY: i8 = 0b0001_0000;
2929
/// Do not negate results before the end of the string
30-
pub const _SIDD_MASKED_POSITIVE_POLARITY: i8 = 0b00100000;
30+
pub const _SIDD_MASKED_POSITIVE_POLARITY: i8 = 0b0010_0000;
3131
/// Negate results only before the end of the string
32-
pub const _SIDD_MASKED_NEGATIVE_POLARITY: i8 = 0b00110000;
32+
pub const _SIDD_MASKED_NEGATIVE_POLARITY: i8 = 0b0011_0000;
3333

3434
/// **Index only**: return the least significant bit *(Default)*
35-
pub const _SIDD_LEAST_SIGNIFICANT: i8 = 0b00000000;
35+
pub const _SIDD_LEAST_SIGNIFICANT: i8 = 0b0000_0000;
3636
/// **Index only**: return the most significant bit
37-
pub const _SIDD_MOST_SIGNIFICANT: i8 = 0b01000000;
37+
pub const _SIDD_MOST_SIGNIFICANT: i8 = 0b0100_0000;
3838

3939
/// **Mask only**: return the bit mask
40-
pub const _SIDD_BIT_MASK: i8 = 0b00000000;
40+
pub const _SIDD_BIT_MASK: i8 = 0b0000_0000;
4141
/// **Mask only**: return the byte mask
42-
pub const _SIDD_UNIT_MASK: i8 = 0b01000000;
42+
pub const _SIDD_UNIT_MASK: i8 = 0b0100_0000;
4343

4444
/// Compare packed strings with implicit lengths in `a` and `b` using the
4545
/// control in `imm8`, and return the generated mask.

‎src/x86/ssse3.rs

+2-1
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,8 @@ pub unsafe fn _mm_shuffle_epi8(a: u8x16, b: u8x16) -> u8x16 {
6868
#[target_feature = "+ssse3"]
6969
#[cfg_attr(test, assert_instr(palignr, n = 15))]
7070
pub unsafe fn _mm_alignr_epi8(a: i8x16, b: i8x16, n: i32) -> i8x16 {
71+
const fn add(a: u32, b: u32) -> u32 { a + b }
72+
7173
let n = n as u32;
7274
// If palignr is shifting the pair of vectors more than the size of two
7375
// lanes, emit zero.
@@ -82,7 +84,6 @@ pub unsafe fn _mm_alignr_epi8(a: i8x16, b: i8x16, n: i32) -> i8x16 {
8284
(a, b, n)
8385
};
8486

85-
const fn add(a: u32, b: u32) -> u32 { a + b }
8687
macro_rules! shuffle {
8788
($shift:expr) => {
8889
simd_shuffle16(b, a, [

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