use simd_shr for vshrq_n_s8 and vshrq_n_u8

Author: SparrowLii

crates/core_arch/src/arm/neon/generated.rs

@@ -8122,6 +8122,18 @@ pub unsafe fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
     simd_shr(a, vdup_n_s8(N.try_into().unwrap()))
 }
 
+/// Shift right
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
+#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sshr, N = 2))]
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
+    static_assert!(N : i32 where N >= 1 && N <= 8);
+    simd_shr(a, vdupq_n_s8(N.try_into().unwrap()))
+}
+
 /// Shift right
 #[inline]
 #[target_feature(enable = "neon")]
@@ -8206,6 +8218,18 @@ pub unsafe fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
     simd_shr(a, vdup_n_u8(N.try_into().unwrap()))
 }
 
+/// Shift right
+#[inline]
+#[target_feature(enable = "neon")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
+#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ushr, N = 2))]
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
+    static_assert!(N : i32 where N >= 1 && N <= 8);
+    simd_shr(a, vdupq_n_u8(N.try_into().unwrap()))
+}
+
 /// Shift right
 #[inline]
 #[target_feature(enable = "neon")]
@@ -14638,6 +14662,14 @@ mod test {
         assert_eq!(r, e);
     }
 
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vshrq_n_s8() {
+        let a: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32);
+        let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8);
+        let r: i8x16 = transmute(vshrq_n_s8::<2>(transmute(a)));
+        assert_eq!(r, e);
+    }
+
     #[simd_test(enable = "neon")]
     unsafe fn test_vshr_n_s16() {
         let a: i16x4 = i16x4::new(4, 8, 12, 16);
@@ -14694,6 +14726,14 @@ mod test {
         assert_eq!(r, e);
     }
 
+    #[simd_test(enable = "neon")]
+    unsafe fn test_vshrq_n_u8() {
+        let a: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32);
+        let e: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8);
+        let r: u8x16 = transmute(vshrq_n_u8::<2>(transmute(a)));
+        assert_eq!(r, e);
+    }
+
     #[simd_test(enable = "neon")]
     unsafe fn test_vshr_n_u16() {
         let a: u16x4 = u16x4::new(4, 8, 12, 16);

crates/core_arch/src/arm/neon/mod.rs

@@ -4412,64 +4412,6 @@ pub unsafe fn vmovq_n_f32(value: f32) -> float32x4_t {
     vdupq_n_f32(value)
 }
 
-/// Signed shift right
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr("sshr", N = 2))]
-#[rustc_legacy_const_generics(1)]
-pub unsafe fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
-    static_assert!(N : i32 where N >= 1 && N <= 8);
-    int8x16_t(
-        a.0 >> N,
-        a.1 >> N,
-        a.2 >> N,
-        a.3 >> N,
-        a.4 >> N,
-        a.5 >> N,
-        a.6 >> N,
-        a.7 >> N,
-        a.8 >> N,
-        a.9 >> N,
-        a.10 >> N,
-        a.11 >> N,
-        a.12 >> N,
-        a.13 >> N,
-        a.14 >> N,
-        a.15 >> N,
-    )
-}
-
-/// Unsigned shift right
-#[inline]
-#[target_feature(enable = "neon")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr("ushr", N = 2))]
-#[rustc_legacy_const_generics(1)]
-pub unsafe fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
-    static_assert!(N : i32 where N >= 1 && N <= 8);
-    uint8x16_t(
-        a.0 >> N,
-        a.1 >> N,
-        a.2 >> N,
-        a.3 >> N,
-        a.4 >> N,
-        a.5 >> N,
-        a.6 >> N,
-        a.7 >> N,
-        a.8 >> N,
-        a.9 >> N,
-        a.10 >> N,
-        a.11 >> N,
-        a.12 >> N,
-        a.13 >> N,
-        a.14 >> N,
-        a.15 >> N,
-    )
-}
-
 /// Extract vector from pair of vectors
 #[inline]
 #[target_feature(enable = "neon")]
@@ -5903,22 +5845,6 @@ mod tests {
         assert_eq!(r, 2);
     }
 
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vshrq_n_s8() {
-        let a = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64);
-        let e = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let r: i8x16 = transmute(vshrq_n_s8::<2>(transmute(a)));
-        assert_eq!(r, e);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vshrq_n_u8() {
-        let a = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64);
-        let e = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-        let r: u8x16 = transmute(vshrq_n_u8::<2>(transmute(a)));
-        assert_eq!(r, e);
-    }
-
     #[simd_test(enable = "neon")]
     unsafe fn test_vext_s64() {
         let a: i64x1 = i64x1::new(0);

crates/stdarch-gen/neon.spec

@@ -2142,9 +2142,9 @@ validate 1, 2, 3, 4, 5, 6, 7, 8
 
 arm = vshr.s
 aarch64 = sshr
-generate int8x8_t, int16x4_t, int16x8_t, int32x2_t, int32x4_t, int64x*_t
+generate int*_t, int64x*_t
 aarch64 = ushr
-generate uint8x8_t, uint16x4_t, uint16x8_t, uint32x2_t, uint32x4_t, uint64x*_t
+generate uint*_t, uint64x*_t
 
 /// Shift right narrow
 name = vshrn_n