feat?(riscv): align misc options (LTO, opt-level)

As with the prior change, the problem we're solving here is shrinking
the state space: there are many branch points within the optmization
machinery, and these settings align with what I've been looking at most
thoroughly.

NB: I have no idea what effect, if any, the Cargo.toml settings have on
downstream crates. Forcing frame pointers in `.cargo/config.toml`
definitely has no effect.

Author: sethp

esp32c3-hal/.cargo/config.toml

@@ -2,6 +2,7 @@
 runner = "espflash flash --monitor"
 rustflags = [
   "-C", "link-arg=-Tlinkall.x",
+  "-C", "force-frame-pointers",
 
   # comment the cfgs below if you do _not_ wish to emulate atomics.
   # enable the atomic codegen option for RISCV

esp32c3-hal/Cargo.toml

@@ -65,10 +65,13 @@ embassy-time-timg0 = ["esp-hal-common/embassy-time-timg0", "embassy-time/tick-hz
 interrupt-preemption = ["esp-hal-common/interrupt-preemption"]
 
 [profile.dev]
-opt-level = 1
+opt-level = 2
+lto = "thin"
 
 [profile.release]
 debug = true
+opt-level = 2
+lto = "thin"
 
 [[example]]
 name              = "spi_eh1_loopback"