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[DAG] NFC: Add getBitcastedExtOrTrunc
Simple function which scalarizes Ops then ExtOrTruncs them according to function parameters Differential Revision: https://reviews.llvm.org/D157733 Change-Id: Ie5215069228f7bf530cd2dbb4bd17cbf409e046a
1 parent 69a6bd5 commit d26a067

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3 files changed

+83
-15
lines changed

3 files changed

+83
-15
lines changed

llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -946,13 +946,44 @@ class SelectionDAG {
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/// integer type VT, by either zero-extending or truncating it.
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SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
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/// Convert Op, which must be of integer type, to the
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/// integer type VT, by either any/sign/zero-extending (depending on IsAny /
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/// IsSigned) or truncating it.
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SDValue getExtOrTrunc(SDValue Op, const SDLoc &DL,
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EVT VT, unsigned Opcode) {
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switch(Opcode) {
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case ISD::ANY_EXTEND:
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return getAnyExtOrTrunc(Op, DL, VT);
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case ISD::ZERO_EXTEND:
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return getZExtOrTrunc(Op, DL, VT);
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case ISD::SIGN_EXTEND:
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return getSExtOrTrunc(Op, DL, VT);
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}
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llvm_unreachable("Unsupported opcode");
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}
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/// Convert Op, which must be of integer type, to the
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/// integer type VT, by either sign/zero-extending (depending on IsSigned) or
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/// truncating it.
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SDValue getExtOrTrunc(bool IsSigned, SDValue Op, const SDLoc &DL, EVT VT) {
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return IsSigned ? getSExtOrTrunc(Op, DL, VT) : getZExtOrTrunc(Op, DL, VT);
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}
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/// Convert Op, which must be of integer type, to the
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/// integer type VT, by first bitcasting (from potential vector) to
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/// corresponding scalar type then either any-extending or truncating it.
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SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
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/// Convert Op, which must be of integer type, to the
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/// integer type VT, by first bitcasting (from potential vector) to
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/// corresponding scalar type then either sign-extending or truncating it.
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SDValue getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
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/// Convert Op, which must be of integer type, to the
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/// integer type VT, by first bitcasting (from potential vector) to
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/// corresponding scalar type then either zero-extending or truncating it.
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SDValue getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
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/// Return the expression required to zero extend the Op
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/// value assuming it was the smaller SrcTy value.
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SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1453,6 +1453,51 @@ SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
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getNode(ISD::TRUNCATE, DL, VT, Op);
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}
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SDValue SelectionDAG::getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL,
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EVT VT) {
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assert(!VT.isVector());
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auto Type = Op.getValueType();
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SDValue DestOp;
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if (Type == VT)
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return Op;
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auto Size = Op.getValueSizeInBits();
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DestOp = getBitcast(MVT::getIntegerVT(Size), Op);
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if (DestOp.getValueType() == VT)
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return DestOp;
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return getAnyExtOrTrunc(DestOp, DL, VT);
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}
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SDValue SelectionDAG::getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL,
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EVT VT) {
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assert(!VT.isVector());
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auto Type = Op.getValueType();
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SDValue DestOp;
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if (Type == VT)
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return Op;
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auto Size = Op.getValueSizeInBits();
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DestOp = getBitcast(MVT::getIntegerVT(Size), Op);
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if (DestOp.getValueType() == VT)
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return DestOp;
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return getSExtOrTrunc(DestOp, DL, VT);
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}
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SDValue SelectionDAG::getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL,
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EVT VT) {
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assert(!VT.isVector());
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auto Type = Op.getValueType();
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SDValue DestOp;
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if (Type == VT)
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return Op;
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auto Size = Op.getValueSizeInBits();
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DestOp = getBitcast(MVT::getIntegerVT(Size), Op);
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if (DestOp.getValueType() == VT)
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return DestOp;
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return getZExtOrTrunc(DestOp, DL, VT);
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}
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SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT,
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EVT OpVT) {
14581503
if (VT.bitsLE(Op.getValueType()))

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 7 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -10943,21 +10943,13 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
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assert(Op.getValueType().isByteSized() &&
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OtherOp.getValueType().isByteSized());
1094510945

10946-
// Handle potential vectors
10947-
Op = DAG.getBitcast(MVT::getIntegerVT(Op.getValueSizeInBits()), Op);
10948-
OtherOp = DAG.getBitcast(
10949-
MVT::getIntegerVT(OtherOp.getValueSizeInBits()), OtherOp);
10950-
10951-
if (Op.getValueSizeInBits() < 32)
10952-
// If the ultimate src is less than 32 bits, then we will only be
10953-
// using bytes 0: Op.getValueSizeInBytes() - 1 in the or.
10954-
// CalculateByteProvider would not have returned Op as source if we
10955-
// used a byte that is outside its ValueType. Thus, we are free to
10956-
// ANY_EXTEND as the extended bits are dont-cares.
10957-
Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op);
10958-
10959-
if (OtherOp.getValueSizeInBits() < 32)
10960-
OtherOp = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, OtherOp);
10946+
// If the ultimate src is less than 32 bits, then we will only be
10947+
// using bytes 0: Op.getValueSizeInBytes() - 1 in the or.
10948+
// CalculateByteProvider would not have returned Op as source if we
10949+
// used a byte that is outside its ValueType. Thus, we are free to
10950+
// ANY_EXTEND as the extended bits are dont-cares.
10951+
Op = DAG.getBitcastedAnyExtOrTrunc(Op, DL, MVT::i32);
10952+
OtherOp = DAG.getBitcastedAnyExtOrTrunc(OtherOp, DL, MVT::i32);
1096110953

1096210954
return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, Op, OtherOp,
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DAG.getConstant(PermMask, DL, MVT::i32));

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