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fpistmfpistm
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Merge pull request #321 from fpistm/HAL_update
Update L4 HAL and CMSIS Drivers to the latest version
2 parents 7eae3be + 9e12729 commit 0f1a0ec

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162 files changed

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‎cores/arduino/stm32/HAL/stm32yyxx_hal_exti.c

+3
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
#ifdef STM32L4xx
2+
#include "stm32l4xx_hal_exti.c"
3+
#endif

‎cores/arduino/stm32/stm32_def_build.h

+4
Original file line numberDiff line numberDiff line change
@@ -247,6 +247,10 @@
247247
#define CMSIS_STARTUP_FILE "startup_stm32l162xdx.s"
248248
#elif defined(STM32L162xE)
249249
#define CMSIS_STARTUP_FILE "startup_stm32l162xe.s"
250+
#elif defined(STM32L412xx)
251+
#define CMSIS_STARTUP_FILE "startup_stm32l412xx.s"
252+
#elif defined(STM32L422xx)
253+
#define CMSIS_STARTUP_FILE "startup_stm32l422xx.s"
250254
#elif defined(STM32L431xx)
251255
#define CMSIS_STARTUP_FILE "startup_stm32l431xx.s"
252256
#elif defined(STM32L432xx)

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h

+10,907
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h

+11,135
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h

+7-4
Original file line numberDiff line numberDiff line change
@@ -711,7 +711,6 @@ typedef struct
711711
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
712712
} RTC_TypeDef;
713713

714-
715714
/**
716715
* @brief Serial Audio Interface
717716
*/
@@ -5672,7 +5671,7 @@ typedef struct
56725671

56735672
/******************* Bit definition for CRC_IDR register ********************/
56745673
#define CRC_IDR_IDR_Pos (0U)
5675-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5674+
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
56765675
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
56775676

56785677
/******************** Bit definition for CRC_CR register ********************/
@@ -7035,15 +7034,15 @@ typedef struct
70357034
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
70367035
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
70377036
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7038-
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7037+
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
70397038
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
70407039

70417040
/****************** Bits definition for FLASH_WRPB1R register ***************/
70427041
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
70437042
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
70447043
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
70457044
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7046-
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7045+
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
70477046
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
70487047

70497048

@@ -9162,6 +9161,8 @@ typedef struct
91629161
/*
91639162
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
91649163
*/
9164+
#define RCC_PLLSAI1_SUPPORT
9165+
#define RCC_PLLP_SUPPORT
91659166
#define RCC_HSI48_SUPPORT
91669167
#define RCC_PLLP_DIV_2_31_SUPPORT
91679168
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
@@ -15039,12 +15040,14 @@ typedef struct
1503915040
/******************************************************************************/
1504015041

1504115042
/* Aliases for __IRQn */
15043+
#define TIM6_IRQn TIM6_DAC_IRQn
1504215044
#define ADC1_2_IRQn ADC1_IRQn
1504315045
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
1504415046
#define HASH_RNG_IRQn RNG_IRQn
1504515047
#define HASH_CRS_IRQn CRS_IRQn
1504615048

1504715049
/* Aliases for __IRQHandler */
15050+
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
1504815051
#define ADC1_2_IRQHandler ADC1_IRQHandler
1504915052
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
1505015053
#define HASH_RNG_IRQHandler RNG_IRQHandler

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h

+7-4
Original file line numberDiff line numberDiff line change
@@ -707,7 +707,6 @@ typedef struct
707707
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
708708
} RTC_TypeDef;
709709

710-
711710
/**
712711
* @brief Serial Audio Interface
713712
*/
@@ -5657,7 +5656,7 @@ typedef struct
56575656

56585657
/******************* Bit definition for CRC_IDR register ********************/
56595658
#define CRC_IDR_IDR_Pos (0U)
5660-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5659+
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
56615660
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
56625661

56635662
/******************** Bit definition for CRC_CR register ********************/
@@ -7038,15 +7037,15 @@ typedef struct
70387037
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
70397038
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
70407039
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7041-
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7040+
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
70427041
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
70437042

70447043
/****************** Bits definition for FLASH_WRPB1R register ***************/
70457044
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
70467045
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
70477046
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
70487047
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7049-
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7048+
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
70507049
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
70517050

70527051

@@ -8820,6 +8819,8 @@ typedef struct
88208819
/*
88218820
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
88228821
*/
8822+
#define RCC_PLLSAI1_SUPPORT
8823+
#define RCC_PLLP_SUPPORT
88238824
#define RCC_HSI48_SUPPORT
88248825
#define RCC_PLLP_DIV_2_31_SUPPORT
88258826
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
@@ -14828,13 +14829,15 @@ typedef struct
1482814829
/******************************************************************************/
1482914830

1483014831
/* Aliases for __IRQn */
14832+
#define TIM6_IRQn TIM6_DAC_IRQn
1483114833
#define ADC1_2_IRQn ADC1_IRQn
1483214834
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
1483314835
#define HASH_RNG_IRQn RNG_IRQn
1483414836
#define HASH_CRS_IRQn CRS_IRQn
1483514837
#define USB_FS_IRQn USB_IRQn
1483614838

1483714839
/* Aliases for __IRQHandler */
14840+
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
1483814841
#define ADC1_2_IRQHandler ADC1_IRQHandler
1483914842
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
1484014843
#define HASH_RNG_IRQHandler RNG_IRQHandler

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h

+7-4
Original file line numberDiff line numberDiff line change
@@ -727,7 +727,6 @@ typedef struct
727727
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
728728
} RTC_TypeDef;
729729

730-
731730
/**
732731
* @brief Serial Audio Interface
733732
*/
@@ -5731,7 +5730,7 @@ typedef struct
57315730

57325731
/******************* Bit definition for CRC_IDR register ********************/
57335732
#define CRC_IDR_IDR_Pos (0U)
5734-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5733+
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
57355734
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
57365735

57375736
/******************** Bit definition for CRC_CR register ********************/
@@ -7118,15 +7117,15 @@ typedef struct
71187117
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
71197118
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
71207119
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7121-
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7120+
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
71227121
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
71237122

71247123
/****************** Bits definition for FLASH_WRPB1R register ***************/
71257124
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
71267125
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
71277126
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
71287127
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7129-
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7128+
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
71307129
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
71317130

71327131

@@ -9254,6 +9253,8 @@ typedef struct
92549253
/*
92559254
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
92569255
*/
9256+
#define RCC_PLLSAI1_SUPPORT
9257+
#define RCC_PLLP_SUPPORT
92579258
#define RCC_HSI48_SUPPORT
92589259
#define RCC_PLLP_DIV_2_31_SUPPORT
92599260
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
@@ -15935,13 +15936,15 @@ typedef struct
1593515936
/******************************************************************************/
1593615937

1593715938
/* Aliases for __IRQn */
15939+
#define TIM6_IRQn TIM6_DAC_IRQn
1593815940
#define ADC1_2_IRQn ADC1_IRQn
1593915941
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
1594015942
#define HASH_RNG_IRQn RNG_IRQn
1594115943
#define HASH_CRS_IRQn CRS_IRQn
1594215944
#define USB_FS_IRQn USB_IRQn
1594315945

1594415946
/* Aliases for __IRQHandler */
15947+
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
1594515948
#define ADC1_2_IRQHandler ADC1_IRQHandler
1594615949
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
1594715950
#define HASH_RNG_IRQHandler RNG_IRQHandler

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h

+7-4
Original file line numberDiff line numberDiff line change
@@ -708,7 +708,6 @@ typedef struct
708708
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
709709
} RTC_TypeDef;
710710

711-
712711
/**
713712
* @brief Serial Audio Interface
714713
*/
@@ -5692,7 +5691,7 @@ typedef struct
56925691

56935692
/******************* Bit definition for CRC_IDR register ********************/
56945693
#define CRC_IDR_IDR_Pos (0U)
5695-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5694+
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
56965695
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
56975696

56985697
/******************** Bit definition for CRC_CR register ********************/
@@ -7254,15 +7253,15 @@ typedef struct
72547253
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
72557254
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
72567255
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7257-
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7256+
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
72587257
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
72597258

72607259
/****************** Bits definition for FLASH_WRPB1R register ***************/
72617260
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
72627261
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
72637262
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
72647263
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7265-
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7264+
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
72667265
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
72677266

72687267

@@ -9036,6 +9035,8 @@ typedef struct
90369035
/*
90379036
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
90389037
*/
9038+
#define RCC_PLLSAI1_SUPPORT
9039+
#define RCC_PLLP_SUPPORT
90399040
#define RCC_HSI48_SUPPORT
90409041
#define RCC_PLLP_DIV_2_31_SUPPORT
90419042
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
@@ -15056,13 +15057,15 @@ typedef struct
1505615057
/******************************************************************************/
1505715058

1505815059
/* Aliases for __IRQn */
15060+
#define TIM6_IRQn TIM6_DAC_IRQn
1505915061
#define ADC1_2_IRQn ADC1_IRQn
1506015062
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
1506115063
#define HASH_RNG_IRQn RNG_IRQn
1506215064
#define HASH_CRS_IRQn CRS_IRQn
1506315065
#define USB_FS_IRQn USB_IRQn
1506415066

1506515067
/* Aliases for __IRQHandler */
15068+
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
1506615069
#define ADC1_2_IRQHandler ADC1_IRQHandler
1506715070
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
1506815071
#define HASH_RNG_IRQHandler RNG_IRQHandler

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h

+7-4
Original file line numberDiff line numberDiff line change
@@ -728,7 +728,6 @@ typedef struct
728728
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
729729
} RTC_TypeDef;
730730

731-
732731
/**
733732
* @brief Serial Audio Interface
734733
*/
@@ -5766,7 +5765,7 @@ typedef struct
57665765

57675766
/******************* Bit definition for CRC_IDR register ********************/
57685767
#define CRC_IDR_IDR_Pos (0U)
5769-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5768+
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
57705769
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
57715770

57725771
/******************** Bit definition for CRC_CR register ********************/
@@ -7334,15 +7333,15 @@ typedef struct
73347333
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
73357334
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
73367335
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7337-
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7336+
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
73387337
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
73397338

73407339
/****************** Bits definition for FLASH_WRPB1R register ***************/
73417340
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
73427341
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
73437342
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
73447343
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7345-
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7344+
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
73467345
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
73477346

73487347

@@ -9470,6 +9469,8 @@ typedef struct
94709469
/*
94719470
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
94729471
*/
9472+
#define RCC_PLLSAI1_SUPPORT
9473+
#define RCC_PLLP_SUPPORT
94739474
#define RCC_HSI48_SUPPORT
94749475
#define RCC_PLLP_DIV_2_31_SUPPORT
94759476
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
@@ -16163,13 +16164,15 @@ typedef struct
1616316164
/******************************************************************************/
1616416165

1616516166
/* Aliases for __IRQn */
16167+
#define TIM6_IRQn TIM6_DAC_IRQn
1616616168
#define ADC1_2_IRQn ADC1_IRQn
1616716169
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
1616816170
#define HASH_RNG_IRQn RNG_IRQn
1616916171
#define HASH_CRS_IRQn CRS_IRQn
1617016172
#define USB_FS_IRQn USB_IRQn
1617116173

1617216174
/* Aliases for __IRQHandler */
16175+
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
1617316176
#define ADC1_2_IRQHandler ADC1_IRQHandler
1617416177
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
1617516178
#define HASH_RNG_IRQHandler RNG_IRQHandler

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h

+7-4
Original file line numberDiff line numberDiff line change
@@ -750,7 +750,6 @@ typedef struct
750750
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
751751
} RTC_TypeDef;
752752

753-
754753
/**
755754
* @brief Serial Audio Interface
756755
*/
@@ -5722,7 +5721,7 @@ typedef struct
57225721

57235722
/******************* Bit definition for CRC_IDR register ********************/
57245723
#define CRC_IDR_IDR_Pos (0U)
5725-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5724+
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
57265725
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
57275726

57285727
/******************** Bit definition for CRC_CR register ********************/
@@ -7292,15 +7291,15 @@ typedef struct
72927291
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
72937292
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
72947293
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7295-
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
7294+
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
72967295
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
72977296

72987297
/****************** Bits definition for FLASH_WRPB1R register ***************/
72997298
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
73007299
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
73017300
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
73027301
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7303-
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
7302+
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
73047303
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
73057304

73067305

@@ -9413,6 +9412,8 @@ typedef struct
94139412
/*
94149413
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
94159414
*/
9415+
#define RCC_PLLSAI1_SUPPORT
9416+
#define RCC_PLLP_SUPPORT
94169417
#define RCC_HSI48_SUPPORT
94179418
#define RCC_PLLP_DIV_2_31_SUPPORT
94189419
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
@@ -15296,6 +15297,7 @@ typedef struct
1529615297
/******************************************************************************/
1529715298

1529815299
/* Aliases for __IRQn */
15300+
#define TIM6_IRQn TIM6_DAC_IRQn
1529915301
#define ADC1_2_IRQn ADC1_IRQn
1530015302
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
1530115303
#define HASH_RNG_IRQn RNG_IRQn
@@ -15304,6 +15306,7 @@ typedef struct
1530415306
#define DFSDM1_IRQn DFSDM1_FLT1_IRQn
1530515307

1530615308
/* Aliases for __IRQHandler */
15309+
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
1530715310
#define ADC1_2_IRQHandler ADC1_IRQHandler
1530815311
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
1530915312
#define HASH_RNG_IRQHandler RNG_IRQHandler

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