system: Restore HSI clock at SystemInit()

ABOSTM · ABOSTM · commit 1559816ce841 · 2022-02-10T15:09:48.000+01:00
When USART Bootloader jumps to application,
PLL is used as System Clock. It prevents to reconfigure PLL.
It is necessary to switch back to default Clock (reset value)
before any further PLL configuration.

Signed-off-by: Alexandre Bourdiol &lt;alexandre.bourdiol@st.com&gt;
diff --git a/system/STM32F0xx/system_stm32f0xx.c b/system/STM32F0xx/system_stm32f0xx.c
@@ -184,10 +184,10 @@ void SystemInit(void)
 #endif
 
   /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
 
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = (uint32_t)0x00BF0000;
 
 }
 
diff --git a/system/STM32F2xx/system_stm32f2xx.c b/system/STM32F2xx/system_stm32f2xx.c
@@ -136,19 +136,19 @@ void SystemInit(void)
   RCC->CR |= (uint32_t)0x00000001;
 
   /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
+  RCC->CFGR = (uint32_t)0x00000000;
 
   /* Reset HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xFEF6FFFF;
 
   /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
+  RCC->PLLCFGR = (uint32_t)0x24003010;
 
   /* Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
 
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = (uint32_t)0x00BF0000;
 
 #ifdef DATA_IN_ExtSRAM
   SystemInit_ExtMemCtl();
diff --git a/system/STM32F3xx/system_stm32f3xx.c b/system/STM32F3xx/system_stm32f3xx.c
@@ -190,8 +190,8 @@ void SystemInit(void)
   /* Reset USARTSW[1:0], I2CSW and TIMs bits */
   RCC->CFGR3 &= 0xFF00FCCCU;
 
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000U;
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
 
   /* Configure the Vector Table location -------------------------------------*/
 #if defined(USER_VECT_TAB_ADDRESS)
diff --git a/system/STM32F4xx/system_stm32f4xx.c b/system/STM32F4xx/system_stm32f4xx.c
@@ -171,19 +171,22 @@ void SystemInit(void)
   RCC->CR |= (uint32_t)0x00000001;
 
   /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
+  RCC->CFGR = (uint32_t)0x00000000;
 
   /* Reset HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xFEF6FFFF;
 
   /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
+  RCC->PLLCFGR = (uint32_t)0x24003010;
 
   /* Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
 
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
+#if defined(RCC_CIR_PLLSAIRDYC)
+  RCC->CIR = (uint32_t)0x00FF0000;
+#else
+  RCC->CIR = (uint32_t)0x00BF0000;
+#endif
 
 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
   SystemInit_ExtMemCtl();
diff --git a/system/STM32F7xx/system_stm32f7xx.c b/system/STM32F7xx/system_stm32f7xx.c
@@ -152,19 +152,19 @@ void SystemInit(void)
   RCC->CR |= (uint32_t)0x00000001;
 
   /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
+  RCC->CFGR = (uint32_t)0x00000000;
 
   /* Reset HSEON, CSSON and PLLON bits */
   RCC->CR &= (uint32_t)0xFEF6FFFF;
 
   /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
+  RCC->PLLCFGR = (uint32_t)0x24003010;
 
   /* Reset HSEBYP bit */
   RCC->CR &= (uint32_t)0xFFFBFFFF;
 
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = (uint32_t)0x00FF0000;
 
 
   /* Configure the Vector Table location -------------------------------------*/
diff --git a/system/STM32G0xx/system_stm32g0xx.c b/system/STM32G0xx/system_stm32g0xx.c
@@ -171,6 +171,31 @@
   */
 void SystemInit(void)
 {
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= 0x00000500U;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000U;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00001000U;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts and clar flags */
+  RCC->CIER = 0x00000000U;
+
+#if defined(RCC_CICR_HSI48RDYC)
+  RCC->CICR = 0x0000033FU;
+#else
+  RCC->CICR = 0x0000033BU;
+#endif
+
   /* Configure the Vector Table location -------------------------------------*/
 #if defined(USER_VECT_TAB_ADDRESS)
   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
diff --git a/system/STM32G4xx/system_stm32g4xx.c b/system/STM32G4xx/system_stm32g4xx.c
@@ -177,6 +177,23 @@ void SystemInit(void)
     SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
   #endif
 
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= 0x00000500U;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000001U;
+
+  /* Reset CR register */
+  RCC->CR = 0x00000500U;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00001000U;
+
+  /* Disable all interrupts and clar flags */
+  RCC->CIER = 0x00000000U;
+  RCC->CICR = 0x0000073BU;
+
   /* Configure the Vector Table location add offset address ------------------*/
 #if defined(USER_VECT_TAB_ADDRESS)
   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
diff --git a/system/STM32H7xx/system_stm32h7xx.c b/system/STM32H7xx/system_stm32h7xx.c
@@ -187,7 +187,7 @@ void SystemInit (void)
   RCC->CR |= RCC_CR_HSION;
 
   /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
+  RCC->CFGR = 0x00000000U;
 
   /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
   RCC->CR &= 0xEAF6ED7FU;
@@ -201,50 +201,51 @@ void SystemInit (void)
 
 #if defined(D3_SRAM_BASE)
   /* Reset D1CFGR register */
-  RCC->D1CFGR = 0x00000000;
+  RCC->D1CFGR = 0x00000000U;
 
   /* Reset D2CFGR register */
-  RCC->D2CFGR = 0x00000000;
+  RCC->D2CFGR = 0x00000000U;
 
   /* Reset D3CFGR register */
-  RCC->D3CFGR = 0x00000000;
+  RCC->D3CFGR = 0x00000000U;
 #else
   /* Reset CDCFGR1 register */
-  RCC->CDCFGR1 = 0x00000000;
+  RCC->CDCFGR1 = 0x00000000U;
 
   /* Reset CDCFGR2 register */
-  RCC->CDCFGR2 = 0x00000000;
+  RCC->CDCFGR2 = 0x00000000U;
 
   /* Reset SRDCFGR register */
-  RCC->SRDCFGR = 0x00000000;
+  RCC->SRDCFGR = 0x00000000U;
 #endif
   /* Reset PLLCKSELR register */
-  RCC->PLLCKSELR = 0x02020200;
+  RCC->PLLCKSELR = 0x02020200U;
 
   /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x01FF0000;
+  RCC->PLLCFGR = 0x01FF0000U;
   /* Reset PLL1DIVR register */
-  RCC->PLL1DIVR = 0x01010280;
+  RCC->PLL1DIVR = 0x01010280U;
   /* Reset PLL1FRACR register */
-  RCC->PLL1FRACR = 0x00000000;
+  RCC->PLL1FRACR = 0x00000000U;
 
   /* Reset PLL2DIVR register */
-  RCC->PLL2DIVR = 0x01010280;
+  RCC->PLL2DIVR = 0x01010280U;
 
   /* Reset PLL2FRACR register */
 
-  RCC->PLL2FRACR = 0x00000000;
+  RCC->PLL2FRACR = 0x00000000U;
   /* Reset PLL3DIVR register */
-  RCC->PLL3DIVR = 0x01010280;
+  RCC->PLL3DIVR = 0x01010280U;
 
   /* Reset PLL3FRACR register */
-  RCC->PLL3FRACR = 0x00000000;
+  RCC->PLL3FRACR = 0x00000000U;
 
   /* Reset HSEBYP bit */
   RCC->CR &= 0xFFFBFFFFU;
 
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
+  /* Disable all interrupts and clar flags */
+  RCC->CIER = 0x00000000U;
+  RCC->CICR = 0x000007FFU;
 
 #if (STM32H7_DEV_ID == 0x450UL)
   /* dual core CM7 or single core line */
diff --git a/system/STM32L0xx/system_stm32l0xx.c b/system/STM32L0xx/system_stm32l0xx.c
@@ -144,25 +144,32 @@ define USER_VECT_TAB_ADDRESS
 void SystemInit (void)
 {    
 /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100U;
+  RCC->CR |= 0x00000100U;
 
   /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400CU;
+  RCC->CFGR =  0x00000000U;
  
   /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6U;
+  RCC->CR = 0x00000100U;
   
   /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+  RCC->CRRCR &= 0xFFFFFFFEU;
   
   /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+  RCC->CR &= 0xFFFBFFFFU;
 
   /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+  RCC->CFGR &= 0xFF02FFFFU;
 
-  /*!< Disable all interrupts */
+  /* Disable all interrupts and clar flags */
   RCC->CIER = 0x00000000U;
+#if defined(RCC_CICR_HSI48RDYC)
+  RCC->CICR = 0x000001FF;
+#elif (RCC_CICR_CSSHSEC)
+  RCC->CICR = 0x000001BFU;
+#else
+  RCC->CICR = 0x000000BFU;
+#endif
   
   /* Configure the Vector Table location add offset address ------------------*/
 #if defined (USER_VECT_TAB_ADDRESS)
diff --git a/system/STM32L1xx/system_stm32l1xx.c b/system/STM32L1xx/system_stm32l1xx.c
@@ -169,8 +169,12 @@ void SystemInit (void)
   /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
   RCC->CFGR &= (uint32_t)0xFF02FFFF;
 
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
+  /* Disable all interrupts and clear pending bits  */
+#if defined(RCC_CIR_LSECSSF)
+  RCC->CIR = (uint32_t)0x00FF0000;
+#else
+  RCC->CIR = (uint32_t)0x00BF0000;
+#endif
 
 #ifdef DATA_IN_ExtSRAM
   SystemInit_ExtMemCtl();
diff --git a/system/STM32L4xx/system_stm32l4xx.c b/system/STM32L4xx/system_stm32l4xx.c
@@ -211,8 +211,19 @@ void SystemInit(void)
   /* Reset HSEBYP bit */
   RCC->CR &= 0xFFFBFFFFU;
 
-  /* Disable all interrupts */
+  /* Disable all interrupts and clar flags */
   RCC->CIER = 0x00000000U;
+#if defined(RCC_CICR_PLLSAI2RDYC)
+#if defined(RCC_CICR_HSI48RDYC)
+  RCC->CICR = 0x000007FFU;
+#else
+  RCC->CICR = 0x000003FFU;
+#endif /* RCC_CICR_HSI48RDYC */
+#elif defined(RCC_CICR_PLLSAI1RDYC)
+  RCC->CICR = 0x0000077FU;
+#else
+  RCC->CICR = 0x0000073FU;
+#endif /* RCC_CICR_PLLSAI2RDYC */
 }
 
 /**
diff --git a/system/STM32L5xx/system_stm32l5xx_ns.c b/system/STM32L5xx/system_stm32l5xx_ns.c
@@ -157,6 +157,26 @@ void SystemInit(void)
   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
 #endif
 
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set MSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset CR register */
+  RCC->CR = 0x00000061U;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00001000U;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts and clar flags */
+  RCC->CIER = 0x00000000U;
+  RCC->CICR = 0x000005FFU;
+
   /* FPU settings ------------------------------------------------------------*/
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
   SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
diff --git a/system/STM32U5xx/system_stm32u5xx.c b/system/STM32U5xx/system_stm32u5xx.c
@@ -206,8 +206,9 @@ void SystemInit(void)
   /* Reset HSEBYP bit */
   RCC->CR &= ~(RCC_CR_HSEBYP);
 
-  /* Disable all interrupts */
-  RCC->CIER = 0U;
+  /* Disable all interrupts and clar flags */
+  RCC->CIER = 0x00000000U;
+  RCC->CICR = 0x00001DFFU;
 
   /* Configure the Vector Table location add offset address ------------------*/
   #ifdef VECT_TAB_SRAM
diff --git a/system/STM32WBxx/system_stm32wbxx.c b/system/STM32WBxx/system_stm32wbxx.c
@@ -205,13 +205,13 @@ void SystemInit(void)
   RCC->CFGR = 0x00070000U;
 
   /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
-  RCC->CR &= (uint32_t)0xFAF6FEFBU;
+  RCC->CR &= 0xFAF6FEFBU;
 
   /*!< Reset LSI1 and LSI2 bits */
-  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+  RCC->CSR &= 0xFFFFFFFAU;
   
   /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+  RCC->CRRCR &= 0xFFFFFFFEU;
     
   /* Reset PLLCFGR register */
   RCC->PLLCFGR = 0x22041000U;
@@ -224,8 +224,17 @@ void SystemInit(void)
   /* Reset HSEBYP bit */
   RCC->CR &= 0xFFFBFFFFU;
 
-  /* Disable all interrupts */
-  RCC->CIER = 0x00000000;
+  /* Disable all interrupts and clar flags */
+  RCC->CIER = 0x00000000U;
+#if defined(RCC_CICR_HSI48RDYC)
+#if defined(RCC_CICR_PLLSAI1RDYC)
+  RCC->CICR = 0x00000F7FU;
+#else
+  RCC->CICR = 0x00000F3FU;
+#endif /* RCC_CICR_PLLSAI1RDYC */
+#else
+  RCC->CICR = 0x00000B3FU;
+#endif /* RCC_CICR_HSI48RDYC */
 }
 
 /**
diff --git a/system/STM32WLxx/system_stm32wlxx.c b/system/STM32WLxx/system_stm32wlxx.c
