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system(U5) update STM32U5xx HAL Drivers to v1.1.0
Included in STM32CubeU5 FW v1.1.0 Signed-off-by: Alexandre Bourdiol <[email protected]>
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‎system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+133-3
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,12 @@ extern "C" {
104104
#if defined(STM32H7)
105105
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
106106
#endif /* STM32H7 */
107+
108+
#if defined(STM32U5)
109+
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
110+
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111+
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112+
#endif /* STM32U5 */
107113
/**
108114
* @}
109115
*/
@@ -213,18 +219,20 @@ extern "C" {
213219
* @{
214220
*/
215221
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
222+
#if defined(STM32U5)
223+
#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
224+
#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
225+
#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
226+
#endif /* STM32U5 */
216227
/**
217228
* @}
218229
*/
219230

220231
/** @defgroup CRC_Aliases CRC API aliases
221232
* @{
222233
*/
223-
#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
224-
#else
225234
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
226235
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
227-
#endif
228236
/**
229237
* @}
230238
*/
@@ -408,6 +416,10 @@ extern "C" {
408416
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
409417

410418
#endif /* STM32H7 */
419+
420+
#if defined(STM32U5)
421+
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
422+
#endif /* STM32U5 */
411423
/**
412424
* @}
413425
*/
@@ -653,6 +665,20 @@ extern "C" {
653665
#endif /* STM32F0 || STM32F3 || STM32F1 */
654666

655667
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
668+
669+
#if defined(STM32U5)
670+
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
671+
#endif /* STM32U5 */
672+
/**
673+
* @}
674+
*/
675+
676+
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
677+
* @{
678+
*/
679+
#if defined(STM32U5)
680+
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
681+
#endif /* STM32U5 */
656682
/**
657683
* @}
658684
*/
@@ -890,9 +916,19 @@ extern "C" {
890916
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
891917
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
892918

919+
920+
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
921+
* @{
922+
*/
923+
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
924+
/**
925+
* @}
926+
*/
927+
893928
#if defined(STM32U5)
894929
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
895930
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
931+
#define LPTIM_CHANNEL_ALL 0x00000000U
896932
#endif /* STM32U5 */
897933
/**
898934
* @}
@@ -1232,6 +1268,10 @@ extern "C" {
12321268
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
12331269
#endif
12341270

1271+
#if defined(STM32U5) || defined(STM32MP2)
1272+
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
1273+
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
1274+
#endif
12351275
/**
12361276
* @}
12371277
*/
@@ -1662,6 +1702,79 @@ extern "C" {
16621702

16631703
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
16641704

1705+
#if defined (STM32U5)
1706+
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
1707+
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
1708+
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1709+
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
1710+
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
1711+
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
1712+
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
1713+
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
1714+
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
1715+
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
1716+
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
1717+
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
1718+
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
1719+
1720+
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
1721+
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
1722+
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
1723+
1724+
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
1725+
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
1726+
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
1727+
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
1728+
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
1729+
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
1730+
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
1731+
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
1732+
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
1733+
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
1734+
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
1735+
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
1736+
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
1737+
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
1738+
1739+
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
1740+
1741+
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
1742+
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
1743+
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
1744+
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
1745+
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
1746+
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
1747+
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
1748+
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
1749+
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
1750+
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
1751+
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
1752+
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
1753+
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
1754+
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
1755+
1756+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
1757+
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
1758+
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
1759+
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
1760+
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
1761+
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
1762+
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
1763+
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
1764+
1765+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
1766+
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
1767+
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
1768+
1769+
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
1770+
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
1771+
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
1772+
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
1773+
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
1774+
1775+
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
1776+
#endif
1777+
16651778
/**
16661779
* @}
16671780
*/
@@ -3420,7 +3533,22 @@ extern "C" {
34203533
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
34213534
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
34223535
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
3536+
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
3537+
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
3538+
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
3539+
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
3540+
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3541+
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3542+
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3543+
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3544+
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3545+
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3546+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3547+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3548+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3549+
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
34233550
#endif
3551+
34243552
/**
34253553
* @}
34263554
*/
@@ -3501,12 +3629,14 @@ extern "C" {
35013629
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
35023630
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
35033631

3632+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
35043633
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
35053634
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
35063635
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
35073636

35083637
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
35093638
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
3639+
#endif
35103640

35113641
#if defined(STM32F4) || defined(STM32F2)
35123642
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h

+83-6
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,8 @@ extern HAL_TickFreqTypeDef uwTickFreq;
8080
* @}
8181
*/
8282

83+
84+
8385
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
8486
* @{
8587
*/
@@ -191,6 +193,48 @@ extern HAL_TickFreqTypeDef uwTickFreq;
191193

192194
#endif /* __ARM_FEATURE_CMSE */
193195

196+
#ifdef SYSCFG_OTGHSPHYCR_EN
197+
/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection
198+
* @{
199+
*/
200+
201+
/** @brief OTG HS PHY reference clock frequency selection
202+
*/
203+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (0x00000003U) /*!< OTG_HS PHY reference clock frequency 16Mhz */
204+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 (0x00000008U) /*!< OTG_HS PHY reference clock frequency 19.2Mhz */
205+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (0x00000009U) /*!< OTG_HS PHY reference clock frequency 20Mhz */
206+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (0x0000000AU) /*!< OTG_HS PHY reference clock frequency 24Mhz */
207+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (0x0000000EU) /*!< OTG_HS PHY reference clock frequency 26Mhz */
208+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (0x0000000BU) /*!< OTG_HS PHY reference clock frequency 32Mhz */
209+
/**
210+
* @}
211+
*/
212+
213+
/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down
214+
* @{
215+
*/
216+
217+
/** @brief OTG HS PHY Power Down config
218+
*/
219+
220+
#define SYSCFG_OTG_HS_PHY_POWER_ON (0x00000000U) /*!< PHY state machine, bias and OTG PHY PLL remain powered */
221+
#define SYSCFG_OTG_HS_PHY_POWER_DOWN (0x00000001U) /*!< PHY state machine, bias and OTG PHY PLL are powered down */
222+
223+
/**
224+
* @}
225+
*/
226+
227+
/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable
228+
* @{
229+
*/
230+
231+
#define SYSCFG_OTG_HS_PHY_UNDERRESET (0x00000000U) /*!< PHY under reset*/
232+
#define SYSCFG_OTG_HS_PHY_ENABLE (0x00000001U) /*!< PHY enabled */
233+
234+
/**
235+
* @}
236+
*/
237+
#endif /* SYSCFG_OTGHSPHYCR_EN */
194238
/**
195239
* @}
196240
*/
@@ -263,11 +307,6 @@ extern HAL_TickFreqTypeDef uwTickFreq;
263307
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
264308
#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
265309

266-
#if defined(DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
267-
#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
268-
#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP)
269-
#endif /* DBGMCU_APB1FZR2_DBG_FDCAN_STOP */
270-
271310
#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
272311
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
273312
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
@@ -555,6 +594,30 @@ extern HAL_TickFreqTypeDef uwTickFreq;
555594

556595

557596
#endif /* __ARM_FEATURE_CMSE */
597+
598+
#ifdef SYSCFG_OTGHSPHYCR_EN
599+
#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) ((((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_1) == \
600+
SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \
601+
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_2) == \
602+
SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \
603+
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_3) == \
604+
SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \
605+
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_4) == \
606+
SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \
607+
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_5) == \
608+
SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \
609+
(((__VALUE__) & SYSCFG_OTG_HS_PHY_CLK_SELECT_6) == \
610+
SYSCFG_OTG_HS_PHY_CLK_SELECT_6))
611+
612+
#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) ((((__VALUE__) & SYSCFG_OTG_HS_PHY_POWER_DOWN) == \
613+
SYSCFG_OTG_HS_PHY_POWER_DOWN) || \
614+
(((__VALUE__) & SYSCFG_OTG_HS_PHY_POWER_ON) == \
615+
SYSCFG_OTG_HS_PHY_POWER_ON))
616+
617+
#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) ((((__VALUE__) & SYSCFG_OTG_HS_PHY_UNDERRESET) == \
618+
SYSCFG_OTG_HS_PHY_UNDERRESET) || \
619+
(((__VALUE__) & SYSCFG_OTG_HS_PHY_ENABLE) == SYSCFG_OTG_HS_PHY_ENABLE))
620+
#endif /* SYSCFG_OTGHSPHYCR_EN */
558621
/**
559622
* @}
560623
*/
@@ -636,10 +699,24 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
636699
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
637700
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
638701
void HAL_SYSCFG_DisableVREFBUF(void);
639-
702+
#ifdef SYSCFG_OTGHSPHYCR_EN
703+
void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection);
704+
void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig);
705+
void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig);
706+
#endif /* SYSCFG_OTGHSPHYCR_EN */
640707
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
641708
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
642709

710+
void HAL_SYSCFG_EnableVddCompensationCell(void);
711+
void HAL_SYSCFG_EnableVddIO2CompensationCell(void);
712+
#if defined(SYSCFG_CCCSR_EN3)
713+
void HAL_SYSCFG_EnableVddHSPICompensationCell(void);
714+
#endif /* SYSCFG_CCCSR_EN3 */
715+
void HAL_SYSCFG_DisableVddCompensationCell(void);
716+
void HAL_SYSCFG_DisableVddIO2CompensationCell(void);
717+
#if defined(SYSCFG_CCCSR_EN3)
718+
void HAL_SYSCFG_DisableVddHSPICompensationCell(void);
719+
#endif /* SYSCFG_CCCSR_EN3 */
643720
/**
644721
* @}
645722
*/

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