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system(H5) update STM32H5xx HAL Drivers to v1.4.0
Included in STM32CubeH5 FW v1.4.0 Signed-off-by: Frederic Pillon <[email protected]>
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‎system/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+67-10
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,9 @@ extern "C" {
472472
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
473473
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
474474
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
475+
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
475476
#define PAGESIZE FLASH_PAGE_SIZE
477+
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
476478
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
477479
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
478480
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@@ -601,6 +603,15 @@ extern "C" {
601603
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
602604
#endif /* STM32G4 */
603605

606+
#if defined(STM32U5)
607+
608+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
609+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
610+
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
611+
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
612+
613+
#endif /* STM32U5 */
614+
604615
#if defined(STM32H5)
605616
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
606617
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@@ -806,6 +817,21 @@ extern "C" {
806817
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
807818
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
808819
#endif /* STM32U5 */
820+
821+
#if defined(STM32WBA)
822+
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
823+
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
824+
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
825+
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
826+
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
827+
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
828+
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
829+
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
830+
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
831+
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
832+
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
833+
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
834+
#endif /* STM32WBA */
809835
/**
810836
* @}
811837
*/
@@ -860,6 +886,10 @@ extern "C" {
860886
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
861887
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
862888

889+
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
890+
#define HRTIMInterruptResquests HRTIMInterruptRequests
891+
#endif /* STM32F3 || STM32G4 || STM32H7 */
892+
863893
#if defined(STM32G4)
864894
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
865895
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -997,8 +1027,8 @@ extern "C" {
9971027
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
9981028
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
9991029
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
1000-
10011030
#endif /* STM32F3 */
1031+
10021032
/**
10031033
* @}
10041034
*/
@@ -1249,10 +1279,10 @@ extern "C" {
12491279
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12501280
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12511281

1252-
#if defined(STM32H5) || defined(STM32H7RS)
1282+
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12531283
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12541284
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
1255-
#endif /* STM32H5 || STM32H7RS */
1285+
#endif /* STM32H5 || STM32H7RS || STM32N6 */
12561286

12571287
#if defined(STM32WBA)
12581288
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1264,10 +1294,10 @@ extern "C" {
12641294
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12651295
#endif /* STM32WBA */
12661296

1267-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
1297+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
12681298
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12691299
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
1270-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
1300+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
12711301

12721302
#if defined(STM32F7)
12731303
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1999,12 +2029,12 @@ extern "C" {
19992029
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
20002030
* @{
20012031
*/
2002-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
2032+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
20032033
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
20042034
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
20052035
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
20062036
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
2007-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
2037+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
20082038

20092039
/**
20102040
* @}
@@ -3665,7 +3695,7 @@ extern "C" {
36653695
#endif
36663696

36673697
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3668-
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
3698+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
36693699
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36703700
#else
36713701
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3916,8 +3946,8 @@ extern "C" {
39163946
*/
39173947
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39183948
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3919-
defined (STM32WBA) || defined (STM32H5) || \
3920-
defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
3949+
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \
3950+
defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39213951
#else
39223952
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39233953
#endif
@@ -4211,6 +4241,33 @@ extern "C" {
42114241

42124242
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
42134243
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
4244+
#if defined(STM32U5)
4245+
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
4246+
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
4247+
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
4248+
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
4249+
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
4250+
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
4251+
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
4252+
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
4253+
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
4254+
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
4255+
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
4256+
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
4257+
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
4258+
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
4259+
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
4260+
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
4261+
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
4262+
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
4263+
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
4264+
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
4265+
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
4266+
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
4267+
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
4268+
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
4269+
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
4270+
#endif
42144271
/**
42154272
* @}
42164273
*/

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -320,10 +320,10 @@ extern HAL_TickFreqTypeDef uwTickFreq;
320320
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
321321
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
322322

323-
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
323+
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
324324
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
325325
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
326-
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
326+
#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
327327

328328
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
329329
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h

+30-26
Original file line numberDiff line numberDiff line change
@@ -123,53 +123,49 @@ typedef struct
123123
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
124124
* @{
125125
*/
126-
#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers,
127-
privileged software access to the default memory map is disabled */
128-
#define MPU_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers,
129-
privileged software access to the default memory map is disabled */
130-
#define MPU_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers,
131-
privileged software access to the default memory map is enabled */
132-
#define MPU_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers,
133-
privileged software access to the default memory map is enabled */
126+
#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
127+
#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
128+
#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
129+
#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
134130
/**
135131
* @}
136132
*/
137133

138134
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
139135
* @{
140136
*/
141-
#define MPU_REGION_ENABLE 1U /*!< MPU region enabled */
142-
#define MPU_REGION_DISABLE 0U /*!< MPU region disabled */
137+
#define MPU_REGION_ENABLE 1U /*!< Enable region */
138+
#define MPU_REGION_DISABLE 0U /*!< Disable region */
143139
/**
144140
* @}
145141
*/
146142

147143
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
148144
* @{
149145
*/
150-
#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< MPU region execution permitted (if read permitted) */
151-
#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< MPU region execution not permitted */
146+
#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */
147+
#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */
152148
/**
153149
* @}
154150
*/
155151

156152
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
157153
* @{
158154
*/
159-
#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */
160-
#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< MPU region outer shareable */
161-
#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */
155+
#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */
156+
#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */
157+
#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */
162158
/**
163159
* @}
164160
*/
165161

166162
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
167163
* @{
168164
*/
169-
#define MPU_REGION_PRIV_RW 0U /*!< MPU region Read/write by privileged code only */
170-
#define MPU_REGION_ALL_RW 1U /*!< MPU region Read/write by any privilege level */
171-
#define MPU_REGION_PRIV_RO 2U /*!< MPU region Read-only by privileged code only */
172-
#define MPU_REGION_ALL_RO 3U /*!< MPU region Read-only by any privilege level */
165+
#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */
166+
#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */
167+
#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */
168+
#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */
173169
/**
174170
* @}
175171
*/
@@ -213,18 +209,26 @@ typedef struct
213209
/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
214210
* @{
215211
*/
216-
#define MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */
217-
#define MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */
218-
#define MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */
219-
#define MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */
212+
/* Device memory attributes */
213+
#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */
214+
#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */
215+
#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */
216+
#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */
220217

221-
#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */
218+
/* Normal memory attributes */
219+
/* To set with INNER_OUTER() macro for both inner/outer cache attributes */
220+
221+
/* Non-cacheable memory attribute */
222222
#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */
223-
#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */
224223

224+
/* Cacheable memory attributes: combination of cache write policy, transient and allocation */
225+
/* - cache write policy */
226+
#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */
227+
#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */
228+
/* - transient mode attribute */
225229
#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */
226230
#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */
227-
231+
/* - allocation attribute */
228232
#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */
229233
#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */
230234
#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h

+7-4
Original file line numberDiff line numberDiff line change
@@ -297,10 +297,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
297297
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
298298
* @{
299299
*/
300-
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
301-
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
302-
#define DAC_CHIPCONNECT_BOTH (1UL << 2)
303-
300+
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/
301+
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via
302+
internal paths) and to an external pin. */
303+
#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via
304+
internal paths) and to an external pin.
305+
Note: this connection is not available in mode normal
306+
with buffer disabled. */
304307
/**
305308
* @}
306309
*/

‎system/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -175,7 +175,7 @@ typedef enum
175175
/**
176176
* @brief __RAM_FUNC definition
177177
*/
178-
#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION))
178+
#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION))
179179

180180
/* ARM Compiler
181181
@@ -208,7 +208,7 @@ typedef enum
208208
/**
209209
* @brief __NOINLINE definition
210210
*/
211-
#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ )
211+
#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ )
212212
/* ARM & GNUCompiler
213213
214214
*/

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