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Merge pull request #1603 from ABOSTM/STM32h7_UPDATE_V1.9.1
Stm32h7 update v1.9.1
2 parents 8c7db46 + 96d8d89 commit e2a677a

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‎cores/arduino/stm32/stm32_def_build.h

+4
Original file line numberDiff line numberDiff line change
@@ -232,8 +232,12 @@
232232
#define CMSIS_STARTUP_FILE "startup_stm32h742xx.s"
233233
#elif defined(STM32H743xx)
234234
#define CMSIS_STARTUP_FILE "startup_stm32h743xx.s"
235+
#elif defined(STM32H745xG)
236+
#define CMSIS_STARTUP_FILE "startup_stm32h745xg.s"
235237
#elif defined(STM32H745xx)
236238
#define CMSIS_STARTUP_FILE "startup_stm32h745xx.s"
239+
#elif defined(STM32H747xG)
240+
#define CMSIS_STARTUP_FILE "startup_stm32h747xg.s"
237241
#elif defined(STM32H747xx)
238242
#define CMSIS_STARTUP_FILE "startup_stm32h747xx.s"
239243
#elif defined(STM32H750xx)

‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h

+60-37
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,12 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2019 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -50,7 +49,7 @@ typedef enum
5049
{
5150
/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
5251
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53-
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
52+
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
5453
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
5554
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
5655
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
@@ -213,12 +212,12 @@ typedef enum
213212
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
214213
*/
215214
#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
216-
#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
217-
#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
218-
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
219-
#define __FPU_PRESENT 1 /*!< FPU present */
220-
#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
221-
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
215+
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
216+
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
217+
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
218+
#define __FPU_PRESENT 1U /*!< FPU present */
219+
#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */
220+
#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */
222221
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
223222

224223
/**
@@ -248,10 +247,10 @@ typedef struct
248247
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
249248
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
250249
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
251-
__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
250+
__IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */
252251
__IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
253252
__IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
254-
__IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
253+
__IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */
255254
uint32_t RESERVED2; /*!< Reserved, 0x02C */
256255
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
257256
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
@@ -928,8 +927,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register,
928927
* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
929928
* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
930929
* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
931-
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
932-
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
930+
* IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
931+
* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
933932
* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
934933
*/
935934

@@ -2700,6 +2699,15 @@ typedef struct
27002699
* @{
27012700
*/
27022701

2702+
/** @addtogroup Hardware_Constant_Definition
2703+
* @{
2704+
*/
2705+
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
2706+
2707+
/**
2708+
* @}
2709+
*/
2710+
27032711
/** @addtogroup Peripheral_Registers_Bits_Definition
27042712
* @{
27052713
*/
@@ -10803,7 +10811,7 @@ typedef struct
1080310811

1080410812
/******************* Bits definition for FLASH_ACR register **********************/
1080510813
#define FLASH_ACR_LATENCY_Pos (0U)
10806-
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
10814+
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */
1080710815
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
1080810816
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
1080910817
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
@@ -10813,6 +10821,14 @@ typedef struct
1081310821
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
1081410822
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
1081510823
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
10824+
10825+
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
10826+
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
10827+
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
10828+
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
10829+
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
10830+
10831+
/* Legacy FLASH Latency defines */
1081610832
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
1081710833
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
1081810834
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
@@ -10821,12 +10837,6 @@ typedef struct
1082110837
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
1082210838
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
1082310839
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
10824-
#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
10825-
#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
10826-
#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
10827-
#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
10828-
#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
10829-
1083010840
/******************* Bits definition for FLASH_CR register ***********************/
1083110841
#define FLASH_CR_LOCK_Pos (0U)
1083210842
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
@@ -19268,8 +19278,8 @@ typedef struct
1926819278
#define TIM_CR2_OIS5_Pos (16U)
1926919279
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
1927019280
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
19271-
#define TIM_CR2_OIS6_Pos (17U)
19272-
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
19281+
#define TIM_CR2_OIS6_Pos (18U)
19282+
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
1927319283
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
1927419284

1927519285
#define TIM_CR2_MMS2_Pos (20U)
@@ -19546,8 +19556,8 @@ typedef struct
1954619556
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
1954719557

1954819558
#define TIM_CCMR2_OC3M_Pos (4U)
19549-
#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
19550-
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
19559+
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
19560+
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
1955119561
#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
1955219562
#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
1955319563
#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
@@ -19571,12 +19581,12 @@ typedef struct
1957119581
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
1957219582

1957319583
#define TIM_CCMR2_OC4M_Pos (12U)
19574-
#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
19575-
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
19584+
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
19585+
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
1957619586
#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
1957719587
#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
1957819588
#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
19579-
#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
19589+
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
1958019590

1958119591
#define TIM_CCMR2_OC4CE_Pos (15U)
1958219592
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
@@ -19782,6 +19792,18 @@ typedef struct
1978219792
#define TIM_BDTR_BK2P_Pos (25U)
1978319793
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
1978419794
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
19795+
#define TIM_BDTR_BKDSRM_Pos (26U)
19796+
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
19797+
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarm */
19798+
#define TIM_BDTR_BK2DSRM_Pos (27U)
19799+
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
19800+
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 Disarm */
19801+
#define TIM_BDTR_BKBID_Pos (28U)
19802+
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
19803+
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectional */
19804+
#define TIM_BDTR_BK2BID_Pos (29U)
19805+
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
19806+
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 Bidirectional */
1978519807

1978619808
/******************* Bit definition for TIM_DCR register ********************/
1978719809
#define TIM_DCR_DBA_Pos (0U)
@@ -19816,8 +19838,8 @@ typedef struct
1981619838
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
1981719839

1981819840
#define TIM_CCMR3_OC5M_Pos (4U)
19819-
#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
19820-
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
19841+
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
19842+
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
1982119843
#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
1982219844
#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
1982319845
#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
@@ -19835,12 +19857,12 @@ typedef struct
1983519857
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
1983619858

1983719859
#define TIM_CCMR3_OC6M_Pos (12U)
19838-
#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
19839-
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
19860+
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
19861+
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
1984019862
#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
1984119863
#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
1984219864
#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
19843-
#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
19865+
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
1984419866

1984519867
#define TIM_CCMR3_OC6CE_Pos (15U)
1984619868
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
@@ -23968,6 +23990,7 @@ typedef struct
2396823990
((INSTANCE) == TIM4) || \
2396923991
((INSTANCE) == TIM5) || \
2397023992
((INSTANCE) == TIM8) || \
23993+
((INSTANCE) == TIM12) || \
2397123994
((INSTANCE) == TIM15) || \
2397223995
((INSTANCE) == TIM23) || \
2397323996
((INSTANCE) == TIM24))
@@ -23980,6 +24003,7 @@ typedef struct
2398024003
((INSTANCE) == TIM4) || \
2398124004
((INSTANCE) == TIM5) || \
2398224005
((INSTANCE) == TIM8) || \
24006+
((INSTANCE) == TIM12) || \
2398324007
((INSTANCE) == TIM15) || \
2398424008
((INSTANCE) == TIM23) || \
2398524009
((INSTANCE) == TIM24))
@@ -24231,4 +24255,3 @@ typedef struct
2423124255

2423224256
#endif /* STM32H723xx_H */
2423324257

24234-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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