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Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions."
I thought this might help with another optimization I was thinking about, but I don't think it will. So it just wastes compile time calling computeKnownBits for no benefit. This reverts commit 81b2f95.
1 parent f00941e commit 010f0f0

14 files changed

+551
-551
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1262,11 +1262,11 @@ def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32),
12621262
(SUBW GPR:$rs1, GPR:$rs2)>;
12631263
def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32),
12641264
(SLLIW GPR:$rs1, uimm5:$shamt)>;
1265-
def : Pat<(i64 (srl (zexti32 (i64 GPR:$rs1)), uimm5:$shamt)),
1265+
def : Pat<(i64 (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt)),
12661266
(SRLIW GPR:$rs1, uimm5:$shamt)>;
12671267
def : Pat<(i64 (srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
12681268
(SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
1269-
def : Pat<(i64 (sra (sexti32 (i64 GPR:$rs1)), uimm5:$shamt)),
1269+
def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
12701270
(SRAIW GPR:$rs1, uimm5:$shamt)>;
12711271
def : Pat<(i64 (sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt)),
12721272
(SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;

‎llvm/test/CodeGen/RISCV/alu8.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ define i8 @srli(i8 %a) nounwind {
124124
; RV64I-LABEL: srli:
125125
; RV64I: # %bb.0:
126126
; RV64I-NEXT: andi a0, a0, 192
127-
; RV64I-NEXT: srliw a0, a0, 6
127+
; RV64I-NEXT: srli a0, a0, 6
128128
; RV64I-NEXT: ret
129129
%1 = lshr i8 %a, 6
130130
ret i8 %1

‎llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -499,9 +499,9 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
499499
; RV64I-NEXT: slli a0, a0, 32
500500
; RV64I-NEXT: srli a0, a0, 32
501501
; RV64I-NEXT: or a0, a0, a1
502-
; RV64I-NEXT: srliw a1, a0, 2
502+
; RV64I-NEXT: srli a1, a0, 2
503503
; RV64I-NEXT: or a0, a0, a1
504-
; RV64I-NEXT: srliw a1, a0, 4
504+
; RV64I-NEXT: srli a1, a0, 4
505505
; RV64I-NEXT: or a0, a0, a1
506506
; RV64I-NEXT: srli a1, a0, 8
507507
; RV64I-NEXT: or a0, a0, a1

‎llvm/test/CodeGen/RISCV/copysign-casts.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
357357
; RV64I-NEXT: addi a2, zero, 1
358358
; RV64I-NEXT: slli a2, a2, 31
359359
; RV64I-NEXT: and a1, a1, a2
360-
; RV64I-NEXT: srliw a1, a1, 16
360+
; RV64I-NEXT: srli a1, a1, 16
361361
; RV64I-NEXT: or a0, a0, a1
362362
; RV64I-NEXT: ret
363363
;

‎llvm/test/CodeGen/RISCV/div.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,7 @@ define i8 @udiv8_constant(i8 %a) nounwind {
276276
; RV64IM-NEXT: andi a0, a0, 255
277277
; RV64IM-NEXT: addi a1, zero, 205
278278
; RV64IM-NEXT: mul a0, a0, a1
279-
; RV64IM-NEXT: srliw a0, a0, 10
279+
; RV64IM-NEXT: srli a0, a0, 10
280280
; RV64IM-NEXT: ret
281281
%1 = udiv i8 %a, 5
282282
ret i8 %1
@@ -298,13 +298,13 @@ define i8 @udiv8_pow2(i8 %a) nounwind {
298298
; RV64I-LABEL: udiv8_pow2:
299299
; RV64I: # %bb.0:
300300
; RV64I-NEXT: andi a0, a0, 248
301-
; RV64I-NEXT: srliw a0, a0, 3
301+
; RV64I-NEXT: srli a0, a0, 3
302302
; RV64I-NEXT: ret
303303
;
304304
; RV64IM-LABEL: udiv8_pow2:
305305
; RV64IM: # %bb.0:
306306
; RV64IM-NEXT: andi a0, a0, 248
307-
; RV64IM-NEXT: srliw a0, a0, 3
307+
; RV64IM-NEXT: srli a0, a0, 3
308308
; RV64IM-NEXT: ret
309309
%1 = udiv i8 %a, 8
310310
ret i8 %1
@@ -404,7 +404,7 @@ define i16 @udiv16_constant(i16 %a) nounwind {
404404
; RV64IM-NEXT: lui a1, 13
405405
; RV64IM-NEXT: addiw a1, a1, -819
406406
; RV64IM-NEXT: mul a0, a0, a1
407-
; RV64IM-NEXT: srliw a0, a0, 18
407+
; RV64IM-NEXT: srli a0, a0, 18
408408
; RV64IM-NEXT: ret
409409
%1 = udiv i16 %a, 5
410410
ret i16 %1
@@ -786,7 +786,7 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
786786
; RV64IM-NEXT: srai a0, a0, 56
787787
; RV64IM-NEXT: addi a1, zero, 103
788788
; RV64IM-NEXT: mul a0, a0, a1
789-
; RV64IM-NEXT: sraiw a1, a0, 9
789+
; RV64IM-NEXT: srai a1, a0, 9
790790
; RV64IM-NEXT: srli a0, a0, 15
791791
; RV64IM-NEXT: andi a0, a0, 1
792792
; RV64IM-NEXT: add a0, a1, a0
@@ -935,7 +935,7 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
935935
; RV64IM-NEXT: lui a1, 6
936936
; RV64IM-NEXT: addiw a1, a1, 1639
937937
; RV64IM-NEXT: mul a0, a0, a1
938-
; RV64IM-NEXT: sraiw a1, a0, 17
938+
; RV64IM-NEXT: srai a1, a0, 17
939939
; RV64IM-NEXT: srli a0, a0, 31
940940
; RV64IM-NEXT: andi a0, a0, 1
941941
; RV64IM-NEXT: add a0, a1, a0

‎llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1529,7 +1529,7 @@ define i32 @aext_srliw_sext(i32 signext %a) nounwind {
15291529
define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {
15301530
; RV64I-LABEL: aext_srliw_zext:
15311531
; RV64I: # %bb.0:
1532-
; RV64I-NEXT: srliw a0, a0, 3
1532+
; RV64I-NEXT: srli a0, a0, 3
15331533
; RV64I-NEXT: ret
15341534
%1 = lshr i32 %a, 3
15351535
ret i32 %1
@@ -1556,7 +1556,7 @@ define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {
15561556
define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {
15571557
; RV64I-LABEL: sext_srliw_zext:
15581558
; RV64I: # %bb.0:
1559-
; RV64I-NEXT: srliw a0, a0, 6
1559+
; RV64I-NEXT: srli a0, a0, 6
15601560
; RV64I-NEXT: ret
15611561
%1 = lshr i32 %a, 6
15621562
ret i32 %1
@@ -1583,7 +1583,7 @@ define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {
15831583
define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
15841584
; RV64I-LABEL: zext_srliw_zext:
15851585
; RV64I: # %bb.0:
1586-
; RV64I-NEXT: srliw a0, a0, 9
1586+
; RV64I-NEXT: srli a0, a0, 9
15871587
; RV64I-NEXT: ret
15881588
%1 = lshr i32 %a, 9
15891589
ret i32 %1
@@ -1603,7 +1603,7 @@ define i32 @aext_sraiw_aext(i32 %a) nounwind {
16031603
define i32 @aext_sraiw_sext(i32 signext %a) nounwind {
16041604
; RV64I-LABEL: aext_sraiw_sext:
16051605
; RV64I: # %bb.0:
1606-
; RV64I-NEXT: sraiw a0, a0, 2
1606+
; RV64I-NEXT: srai a0, a0, 2
16071607
; RV64I-NEXT: ret
16081608
%1 = ashr i32 %a, 2
16091609
ret i32 %1
@@ -1630,7 +1630,7 @@ define signext i32 @sext_sraiw_aext(i32 %a) nounwind {
16301630
define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {
16311631
; RV64I-LABEL: sext_sraiw_sext:
16321632
; RV64I: # %bb.0:
1633-
; RV64I-NEXT: sraiw a0, a0, 5
1633+
; RV64I-NEXT: srai a0, a0, 5
16341634
; RV64I-NEXT: ret
16351635
%1 = ashr i32 %a, 5
16361636
ret i32 %1

‎llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -614,25 +614,25 @@ define i8 @srli_i8(i8 %a) nounwind {
614614
; RV64I-LABEL: srli_i8:
615615
; RV64I: # %bb.0:
616616
; RV64I-NEXT: andi a0, a0, 192
617-
; RV64I-NEXT: srliw a0, a0, 6
617+
; RV64I-NEXT: srli a0, a0, 6
618618
; RV64I-NEXT: ret
619619
;
620620
; RV64IB-LABEL: srli_i8:
621621
; RV64IB: # %bb.0:
622622
; RV64IB-NEXT: andi a0, a0, 192
623-
; RV64IB-NEXT: srliw a0, a0, 6
623+
; RV64IB-NEXT: srli a0, a0, 6
624624
; RV64IB-NEXT: ret
625625
;
626626
; RV64IBB-LABEL: srli_i8:
627627
; RV64IBB: # %bb.0:
628628
; RV64IBB-NEXT: andi a0, a0, 192
629-
; RV64IBB-NEXT: srliw a0, a0, 6
629+
; RV64IBB-NEXT: srli a0, a0, 6
630630
; RV64IBB-NEXT: ret
631631
;
632632
; RV64IBP-LABEL: srli_i8:
633633
; RV64IBP: # %bb.0:
634634
; RV64IBP-NEXT: andi a0, a0, 192
635-
; RV64IBP-NEXT: srliw a0, a0, 6
635+
; RV64IBP-NEXT: srli a0, a0, 6
636636
; RV64IBP-NEXT: ret
637637
%1 = lshr i8 %a, 6
638638
ret i8 %1
@@ -648,13 +648,13 @@ define i8 @srai_i8(i8 %a) nounwind {
648648
; RV64IB-LABEL: srai_i8:
649649
; RV64IB: # %bb.0:
650650
; RV64IB-NEXT: sext.b a0, a0
651-
; RV64IB-NEXT: sraiw a0, a0, 5
651+
; RV64IB-NEXT: srai a0, a0, 5
652652
; RV64IB-NEXT: ret
653653
;
654654
; RV64IBB-LABEL: srai_i8:
655655
; RV64IBB: # %bb.0:
656656
; RV64IBB-NEXT: sext.b a0, a0
657-
; RV64IBB-NEXT: sraiw a0, a0, 5
657+
; RV64IBB-NEXT: srai a0, a0, 5
658658
; RV64IBB-NEXT: ret
659659
;
660660
; RV64IBP-LABEL: srai_i8:
@@ -676,19 +676,19 @@ define i16 @srli_i16(i16 %a) nounwind {
676676
; RV64IB-LABEL: srli_i16:
677677
; RV64IB: # %bb.0:
678678
; RV64IB-NEXT: zext.h a0, a0
679-
; RV64IB-NEXT: srliw a0, a0, 6
679+
; RV64IB-NEXT: srli a0, a0, 6
680680
; RV64IB-NEXT: ret
681681
;
682682
; RV64IBB-LABEL: srli_i16:
683683
; RV64IBB: # %bb.0:
684684
; RV64IBB-NEXT: zext.h a0, a0
685-
; RV64IBB-NEXT: srliw a0, a0, 6
685+
; RV64IBB-NEXT: srli a0, a0, 6
686686
; RV64IBB-NEXT: ret
687687
;
688688
; RV64IBP-LABEL: srli_i16:
689689
; RV64IBP: # %bb.0:
690690
; RV64IBP-NEXT: zext.h a0, a0
691-
; RV64IBP-NEXT: srliw a0, a0, 6
691+
; RV64IBP-NEXT: srli a0, a0, 6
692692
; RV64IBP-NEXT: ret
693693
%1 = lshr i16 %a, 6
694694
ret i16 %1
@@ -704,13 +704,13 @@ define i16 @srai_i16(i16 %a) nounwind {
704704
; RV64IB-LABEL: srai_i16:
705705
; RV64IB: # %bb.0:
706706
; RV64IB-NEXT: sext.h a0, a0
707-
; RV64IB-NEXT: sraiw a0, a0, 9
707+
; RV64IB-NEXT: srai a0, a0, 9
708708
; RV64IB-NEXT: ret
709709
;
710710
; RV64IBB-LABEL: srai_i16:
711711
; RV64IBB: # %bb.0:
712712
; RV64IBB-NEXT: sext.h a0, a0
713-
; RV64IBB-NEXT: sraiw a0, a0, 9
713+
; RV64IBB-NEXT: srai a0, a0, 9
714714
; RV64IBB-NEXT: ret
715715
;
716716
; RV64IBP-LABEL: srai_i16:

‎llvm/test/CodeGen/RISCV/rv64zbb.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,9 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
1919
; RV64I-NEXT: slli a0, a0, 32
2020
; RV64I-NEXT: srli a0, a0, 32
2121
; RV64I-NEXT: or a0, a0, a1
22-
; RV64I-NEXT: srliw a1, a0, 2
22+
; RV64I-NEXT: srli a1, a0, 2
2323
; RV64I-NEXT: or a0, a0, a1
24-
; RV64I-NEXT: srliw a1, a0, 4
24+
; RV64I-NEXT: srli a1, a0, 4
2525
; RV64I-NEXT: or a0, a0, a1
2626
; RV64I-NEXT: srli a1, a0, 8
2727
; RV64I-NEXT: or a0, a0, a1
@@ -105,9 +105,9 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
105105
; RV64I-NEXT: slli a0, a0, 32
106106
; RV64I-NEXT: srli a0, a0, 32
107107
; RV64I-NEXT: or a0, a0, a1
108-
; RV64I-NEXT: srliw a1, a0, 2
108+
; RV64I-NEXT: srli a1, a0, 2
109109
; RV64I-NEXT: or a0, a0, a1
110-
; RV64I-NEXT: srliw a1, a0, 4
110+
; RV64I-NEXT: srli a1, a0, 4
111111
; RV64I-NEXT: or a0, a0, a1
112112
; RV64I-NEXT: srli a1, a0, 8
113113
; RV64I-NEXT: or a0, a0, a1
@@ -202,9 +202,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
202202
; RV64I-NEXT: slli a0, a0, 32
203203
; RV64I-NEXT: srli a0, a0, 32
204204
; RV64I-NEXT: or a0, a0, a1
205-
; RV64I-NEXT: srliw a1, a0, 2
205+
; RV64I-NEXT: srli a1, a0, 2
206206
; RV64I-NEXT: or a0, a0, a1
207-
; RV64I-NEXT: srliw a1, a0, 4
207+
; RV64I-NEXT: srli a1, a0, 4
208208
; RV64I-NEXT: or a0, a0, a1
209209
; RV64I-NEXT: srli a1, a0, 8
210210
; RV64I-NEXT: or a0, a0, a1
@@ -295,9 +295,9 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
295295
; RV64I-NEXT: srli a0, a0, 32
296296
; RV64I-NEXT: srliw a1, s0, 1
297297
; RV64I-NEXT: or a0, a0, a1
298-
; RV64I-NEXT: srliw a1, a0, 2
298+
; RV64I-NEXT: srli a1, a0, 2
299299
; RV64I-NEXT: or a0, a0, a1
300-
; RV64I-NEXT: srliw a1, a0, 4
300+
; RV64I-NEXT: srli a1, a0, 4
301301
; RV64I-NEXT: or a0, a0, a1
302302
; RV64I-NEXT: srli a1, a0, 8
303303
; RV64I-NEXT: or a0, a0, a1
@@ -395,11 +395,11 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
395395
; RV64I-NEXT: srliw a0, a0, 1
396396
; RV64I-NEXT: beqz a0, .LBB4_2
397397
; RV64I-NEXT: # %bb.1: # %cond.false
398-
; RV64I-NEXT: srliw a1, a0, 1
398+
; RV64I-NEXT: srli a1, a0, 1
399399
; RV64I-NEXT: or a0, a0, a1
400-
; RV64I-NEXT: srliw a1, a0, 2
400+
; RV64I-NEXT: srli a1, a0, 2
401401
; RV64I-NEXT: or a0, a0, a1
402-
; RV64I-NEXT: srliw a1, a0, 4
402+
; RV64I-NEXT: srli a1, a0, 4
403403
; RV64I-NEXT: or a0, a0, a1
404404
; RV64I-NEXT: srli a1, a0, 8
405405
; RV64I-NEXT: or a0, a0, a1
@@ -1016,7 +1016,7 @@ define signext i32 @ctpop_i32_load(i32* %p) nounwind {
10161016
; RV64I-NEXT: addi sp, sp, -16
10171017
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
10181018
; RV64I-NEXT: lwu a0, 0(a0)
1019-
; RV64I-NEXT: srliw a1, a0, 1
1019+
; RV64I-NEXT: srli a1, a0, 1
10201020
; RV64I-NEXT: lui a2, 349525
10211021
; RV64I-NEXT: addiw a2, a2, 1365
10221022
; RV64I-NEXT: and a1, a1, a2

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