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Revert "[M68k][GloballSel] Formal arguments lowering in IRTranslator"
This reverts commit 8f43407 due to failure on its associated test.
1 parent 616b998 commit 04242bd

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5 files changed

+4
-249
lines changed

5 files changed

+4
-249
lines changed

‎llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

+4-48
Original file line numberDiff line numberDiff line change
@@ -15,17 +15,12 @@
1515
#include "M68kCallLowering.h"
1616
#include "M68kISelLowering.h"
1717
#include "M68kInstrInfo.h"
18-
#include "M68kSubtarget.h"
19-
#include "M68kTargetMachine.h"
20-
#include "llvm/CodeGen/CallingConvLower.h"
21-
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
2218
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
23-
#include "llvm/CodeGen/TargetCallingConv.h"
24-
2519
using namespace llvm;
2620

2721
M68kCallLowering::M68kCallLowering(const M68kTargetLowering &TLI)
2822
: CallLowering(&TLI) {}
23+
2924
bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
3025
const Value *Val, ArrayRef<Register> VRegs,
3126
FunctionLoweringInfo &FLI,
@@ -41,50 +36,11 @@ bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
4136
const Function &F,
4237
ArrayRef<ArrayRef<Register>> VRegs,
4338
FunctionLoweringInfo &FLI) const {
44-
MachineFunction &MF = MIRBuilder.getMF();
45-
MachineRegisterInfo &MRI = MF.getRegInfo();
46-
const auto &DL = F.getParent()->getDataLayout();
47-
auto &TLI = *getTLI<M68kTargetLowering>();
4839

49-
SmallVector<ArgInfo, 8> SplitArgs;
50-
unsigned I = 0;
51-
for (const auto &Arg : F.args()) {
52-
ArgInfo OrigArg{VRegs[I], Arg.getType()};
53-
setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
54-
splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
55-
++I;
56-
}
40+
if (F.arg_empty())
41+
return true;
5742

58-
CCAssignFn *AssignFn =
59-
TLI.getCCAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
60-
IncomingValueAssigner ArgAssigner(AssignFn);
61-
FormalArgHandler ArgHandler(MIRBuilder, MRI);
62-
return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
63-
MIRBuilder, F.getCallingConv(),
64-
F.isVarArg());
65-
}
66-
67-
void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
68-
Register PhysReg,
69-
CCValAssign &VA) {
70-
MIRBuilder.getMRI()->addLiveIn(PhysReg);
71-
MIRBuilder.getMBB().addLiveIn(PhysReg);
72-
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
73-
}
74-
75-
void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
76-
Register Addr,
77-
uint64_t Size,
78-
MachinePointerInfo &MPO,
79-
CCValAssign &VA) {
80-
llvm_unreachable("unimeplemented");
81-
}
82-
83-
Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
84-
int64_t Offset,
85-
MachinePointerInfo &MPO,
86-
ISD::ArgFlagsTy Flags) {
87-
llvm_unreachable("unimeplemented");
43+
return false;
8844
}
8945

9046
bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,

‎llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

-23
Original file line numberDiff line numberDiff line change
@@ -43,29 +43,6 @@ class M68kCallLowering : public CallLowering {
4343

4444
bool enableBigEndian() const override;
4545
};
46-
struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
47-
M68kIncomingValueHandler(MachineIRBuilder &MIRBuilder,
48-
MachineRegisterInfo &MRI)
49-
: CallLowering::IncomingValueHandler(MIRBuilder, MRI) {}
50-
51-
uint64_t StackUsed;
52-
53-
private:
54-
void assignValueToReg(Register ValVReg, Register PhysReg,
55-
CCValAssign &VA) override;
56-
57-
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
58-
MachinePointerInfo &MPO, CCValAssign &VA) override;
59-
60-
Register getStackAddress(uint64_t Size, int64_t Offset,
61-
MachinePointerInfo &MPO,
62-
ISD::ArgFlagsTy Flags) override;
63-
};
64-
65-
struct FormalArgHandler : public M68kIncomingValueHandler {
66-
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
67-
: M68kIncomingValueHandler(MIRBuilder, MRI) {}
68-
};
6946

7047
} // end namespace llvm
7148

‎llvm/lib/Target/M68k/M68kISelLowering.cpp

-6
Original file line numberDiff line numberDiff line change
@@ -3412,9 +3412,3 @@ const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
34123412
return NULL;
34133413
}
34143414
}
3415-
3416-
CCAssignFn *M68kTargetLowering::getCCAssignFnForCall(CallingConv::ID CC,
3417-
bool Return,
3418-
bool IsVarArg) const {
3419-
return CC_M68k_C;
3420-
}

‎llvm/lib/Target/M68k/M68kISelLowering.h

-3
Original file line numberDiff line numberDiff line change
@@ -171,9 +171,6 @@ class M68kTargetLowering : public TargetLowering {
171171
EmitInstrWithCustomInserter(MachineInstr &MI,
172172
MachineBasicBlock *MBB) const override;
173173

174-
CCAssignFn *getCCAssignFnForCall(CallingConv::ID CC, bool Return,
175-
bool IsVarArg) const;
176-
177174
private:
178175
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
179176
SelectionDAG &DAG) const;

‎llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

-169
Original file line numberDiff line numberDiff line change
@@ -1,176 +1,7 @@
11
; RUN: llc -mtriple=m68k -global-isel -stop-after=irtranslator < %s | FileCheck %s
22

3-
%struct.A = type { i8, float, i32, i32, i32 }
4-
53
; CHECK: name: noArgRetVoid
64
; CHECK: RTS
75
define void @noArgRetVoid() {
86
ret void
97
}
10-
11-
define void @test_arg_lowering1(i8 %x, i8 %y) {
12-
; CHECK-LABEL: name: test_arg_lowering1
13-
; CHECK: bb.1 (%ir-block.0):
14-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
15-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
16-
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
17-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
18-
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
19-
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
20-
; CHECK: RTS
21-
ret void
22-
}
23-
24-
define void @test_arg_lowering2(i16 %x, i16 %y) {
25-
; CHECK-LABEL: name: test_arg_lowering2
26-
; CHECK: bb.1 (%ir-block.0):
27-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
28-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
29-
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD1]](s32)
30-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
31-
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
32-
; CHECK: [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD2]](s32)
33-
; CHECK: RTS
34-
ret void
35-
}
36-
37-
define void @test_arg_lowering3(i32 %x, i32 %y) {
38-
; CHECK-LABEL: name: test_arg_lowering3
39-
; CHECK: bb.1 (%ir-block.0):
40-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
41-
; CHECK: {{%.*}} G_LOAD [[G_F_I1]](p0)
42-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
43-
; CHECK: {{%.*}} G_LOAD [[G_F_I2]](p0)
44-
; CHECK: RTS
45-
ret void
46-
}
47-
48-
define void @test_arg_lowering_vector(<5 x i8> %x) {
49-
; CHECK-LABEL: name: test_arg_lowering_vector
50-
; CHECK: bb.1 (%ir-block.0):
51-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
52-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
53-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
54-
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
55-
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
56-
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
57-
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
58-
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
59-
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
60-
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
61-
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[G_LOAD1]](s32), [[G_LOAD2]](s32), [[G_LOAD3]](s32), [[G_LOAD4]](s32), [[G_LOAD5]](s32)
62-
; CHECK: [[G_TRUNC:%[0-9]+]]:_(<5 x s8>) = G_TRUNC [[BUILD_VECTOR]](<5 x s32>)
63-
; CHECK: RTS
64-
ret void
65-
}
66-
67-
define void @test_arg_lowering_array([5 x i8] %x) {
68-
; CHECK-LABEL: name: test_arg_lowering_array
69-
; CHECK: bb.1 (%ir-block.0):
70-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
71-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
72-
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
73-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
74-
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
75-
; CHECK: [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
76-
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
77-
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
78-
; CHECK: [[G_TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD3]](s32)
79-
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
80-
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
81-
; CHECK: [[G_TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD4]](s32)
82-
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
83-
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
84-
; CHECK: [[G_TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD5]](s32)
85-
; CHECK: RTS
86-
ret void
87-
}
88-
89-
define void @test_arg_lowering_double(double %x) {
90-
; CHECK-LABEL: name: test_arg_lowering_double
91-
; CHECK: bb.1 (%ir-block.0):
92-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
93-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
94-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
95-
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
96-
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
97-
; CHECK: RTS
98-
ret void
99-
}
100-
101-
define void @test_arg_lowering_float(float %x) {
102-
; CHECK-LABEL: name: test_arg_lowering_float
103-
; CHECK: bb.1 (%ir-block.0):
104-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
105-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
106-
; CHECK: RTS
107-
ret void
108-
}
109-
110-
define void @test_arg_lowering_multiple(i1 %a, i8 %b, i16 %c, i32 %d, i64 %e, i128 %f){
111-
; CHECK-LABEL: name: test_arg_lowering_multiple
112-
; CHECK: bb.1 (%ir-block.0):
113-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
114-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
115-
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[G_LOAD1]](s32)
116-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
117-
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
118-
; CHECK: [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
119-
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
120-
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
121-
; CHECK: [[G_TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD3]](s32)
122-
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
123-
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
124-
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
125-
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
126-
; CHECK: [[G_F_I6:%[0-9]+]]:_(p0) = G_FRAME_INDEX
127-
; CHECK: [[G_LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I6]](p0)
128-
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD5]](s32), [[G_LOAD6]](s32)
129-
; CHECK: [[G_F_I7:%[0-9]+]]:_(p0) = G_FRAME_INDEX
130-
; CHECK: [[G_LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I7]](p0)
131-
; CHECK: [[G_F_I8:%[0-9]+]]:_(p0) = G_FRAME_INDEX
132-
; CHECK: [[G_LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I8]](p0)
133-
; CHECK: [[G_F_I9:%[0-9]+]]:_(p0) = G_FRAME_INDEX
134-
; CHECK: [[G_LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I9]](p0)
135-
; CHECK: [[G_F_I10:%[0-9]+]]:_(p0) = G_FRAME_INDEX
136-
; CHECK: [[G_LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I10]](p0)
137-
; CHECK: [[G_MERGE_VAL:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[G_LOAD7]](s32), [[G_LOAD8]](s32), [[G_LOAD9]](s32), [[G_LOAD10]](s32)
138-
; CHECK: RTS
139-
ret void
140-
}
141-
142-
define void @test_arg_lowering_ptr(i32* %x) {
143-
; CHECK-LABEL: name: test_arg_lowering_ptr
144-
; CHECK: bb.1 (%ir-block.0):
145-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
146-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
147-
; CHECK: RTS
148-
ret void
149-
}
150-
151-
define void @test_arg_lowering_float_ptr(float* %x) {
152-
; CHECK-LABEL: name: test_arg_lowering_float_ptr
153-
; CHECK: bb.1 (%ir-block.0):
154-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
155-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
156-
; CHECK: RTS
157-
ret void
158-
}
159-
160-
define void @test_arg_lowering_struct(%struct.A %a) #0 {
161-
; CHECK-LABEL: name: test_arg_lowering_struct
162-
; CHECK: bb.1 (%ir-block.0):
163-
; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX
164-
; CHECK: [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
165-
; CHECK: [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
166-
; CHECK: [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX
167-
; CHECK: [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
168-
; CHECK: [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX
169-
; CHECK: [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
170-
; CHECK: [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX
171-
; CHECK: [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
172-
; CHECK: [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX
173-
; CHECK: [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
174-
; CHECK: RTS
175-
ret void
176-
}

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