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[RISCV] Expand rotate by non-constant for XTHeadBb during lowering.
Avoids multi instruction isel patterns and enables mask optimizations on shift amount. Reviewed By: philipp.tomsich Differential Revision: https://reviews.llvm.org/D151263
1 parent 429e748 commit 1f7c174

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3 files changed

+60
-64
lines changed

3 files changed

+60
-64
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -285,10 +285,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
285285
setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, XLenVT,
286286
Custom);
287287

288-
if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
289-
Subtarget.hasVendorXTHeadBb()) {
288+
if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) {
290289
if (Subtarget.is64Bit())
291290
setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
291+
} else if (Subtarget.hasVendorXTHeadBb()) {
292+
if (Subtarget.is64Bit())
293+
setOperationAction({ISD::ROTL, ISD::ROTR}, MVT::i32, Custom);
294+
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Custom);
292295
} else {
293296
setOperationAction({ISD::ROTL, ISD::ROTR}, XLenVT, Expand);
294297
}
@@ -4418,6 +4421,15 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
44184421
return lowerShiftRightParts(Op, DAG, true);
44194422
case ISD::SRL_PARTS:
44204423
return lowerShiftRightParts(Op, DAG, false);
4424+
case ISD::ROTL:
4425+
case ISD::ROTR:
4426+
assert(Subtarget.hasVendorXTHeadBb() &&
4427+
!(Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()) &&
4428+
"Unexpected custom legalization");
4429+
// XTHeadBb only supports rotate by constant.
4430+
if (!isa<ConstantSDNode>(Op.getOperand(1)))
4431+
return SDValue();
4432+
return Op;
44214433
case ISD::BITCAST: {
44224434
SDLoc DL(Op);
44234435
EVT VT = Op.getValueType();
@@ -9032,6 +9044,12 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
90329044
case ISD::ROTR:
90339045
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
90349046
"Unexpected custom legalisation");
9047+
assert((Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb() ||
9048+
Subtarget.hasVendorXTHeadBb()) &&
9049+
"Unexpected custom legalization");
9050+
if (!isa<ConstantSDNode>(N->getOperand(1)) &&
9051+
!(Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbkb()))
9052+
return;
90359053
Results.push_back(customLegalizeToWOp(N, DAG));
90369054
break;
90379055
case ISD::CTTZ:

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -598,12 +598,6 @@ def : PatGprImm<rotr, TH_SRRI, uimmlog2xlen>;
598598
// it can be implemented with th.srri by negating the immediate.
599599
def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
600600
(TH_SRRI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
601-
def : Pat<(rotr GPR:$rs1, GPR:$rs2),
602-
(OR (SRL GPR:$rs1, GPR:$rs2),
603-
(SLL GPR:$rs1, (SUB X0, GPR:$rs2)))>;
604-
def : Pat<(rotl GPR:$rs1, GPR:$rs2),
605-
(OR (SLL GPR:$rs1, GPR:$rs2),
606-
(SRL GPR:$rs1, (SUB X0, GPR:$rs2)))>;
607601
def : Pat<(sext_inreg GPR:$rs1, i32), (TH_EXT GPR:$rs1, 31, 0)>;
608602
def : Pat<(sext_inreg GPR:$rs1, i16), (TH_EXT GPR:$rs1, 15, 0)>;
609603
def : Pat<(sext_inreg GPR:$rs1, i8), (TH_EXT GPR:$rs1, 7, 0)>;
@@ -617,12 +611,6 @@ let Predicates = [HasVendorXTHeadBb, IsRV64] in {
617611
def : PatGprImm<riscv_rorw, TH_SRRIW, uimm5>;
618612
def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
619613
(TH_SRRIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
620-
def : Pat<(riscv_rorw i64:$rs1, i64:$rs2),
621-
(OR (SRLW i64:$rs1, i64:$rs2),
622-
(SLLW i64:$rs1, (SUB X0, i64:$rs2)))>;
623-
def : Pat<(riscv_rolw i64:$rs1, i64:$rs2),
624-
(OR (SLLW i64:$rs1, i64:$rs2),
625-
(SRLW i64:$rs1, (SUB X0, i64:$rs2)))>;
626614
def : Pat<(sra (bswap i64:$rs1), (i64 32)),
627615
(TH_REVW i64:$rs1)>;
628616
def : Pat<(binop_allwusers<srl> (bswap i64:$rs1), (i64 32)),

‎llvm/test/CodeGen/RISCV/rotl-rotr.ll

Lines changed: 40 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ define i32 @rotl_32(i32 %x, i32 %y) nounwind {
5656
; RV64XTHEADBB-LABEL: rotl_32:
5757
; RV64XTHEADBB: # %bb.0:
5858
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
59-
; RV64XTHEADBB-NEXT: neg a1, a1
59+
; RV64XTHEADBB-NEXT: negw a1, a1
6060
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
6161
; RV64XTHEADBB-NEXT: or a0, a2, a0
6262
; RV64XTHEADBB-NEXT: ret
@@ -105,7 +105,7 @@ define i32 @rotr_32(i32 %x, i32 %y) nounwind {
105105
; RV64XTHEADBB-LABEL: rotr_32:
106106
; RV64XTHEADBB: # %bb.0:
107107
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
108-
; RV64XTHEADBB-NEXT: neg a1, a1
108+
; RV64XTHEADBB-NEXT: negw a1, a1
109109
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
110110
; RV64XTHEADBB-NEXT: or a0, a2, a0
111111
; RV64XTHEADBB-NEXT: ret
@@ -253,7 +253,7 @@ define i64 @rotl_64(i64 %x, i64 %y) nounwind {
253253
; RV64XTHEADBB-LABEL: rotl_64:
254254
; RV64XTHEADBB: # %bb.0:
255255
; RV64XTHEADBB-NEXT: sll a2, a0, a1
256-
; RV64XTHEADBB-NEXT: neg a1, a1
256+
; RV64XTHEADBB-NEXT: negw a1, a1
257257
; RV64XTHEADBB-NEXT: srl a0, a0, a1
258258
; RV64XTHEADBB-NEXT: or a0, a2, a0
259259
; RV64XTHEADBB-NEXT: ret
@@ -401,7 +401,7 @@ define i64 @rotr_64(i64 %x, i64 %y) nounwind {
401401
; RV64XTHEADBB-LABEL: rotr_64:
402402
; RV64XTHEADBB: # %bb.0:
403403
; RV64XTHEADBB-NEXT: srl a2, a0, a1
404-
; RV64XTHEADBB-NEXT: neg a1, a1
404+
; RV64XTHEADBB-NEXT: negw a1, a1
405405
; RV64XTHEADBB-NEXT: sll a0, a0, a1
406406
; RV64XTHEADBB-NEXT: or a0, a2, a0
407407
; RV64XTHEADBB-NEXT: ret
@@ -450,7 +450,7 @@ define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {
450450
; RV64XTHEADBB-LABEL: rotl_32_mask:
451451
; RV64XTHEADBB: # %bb.0:
452452
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
453-
; RV64XTHEADBB-NEXT: neg a1, a1
453+
; RV64XTHEADBB-NEXT: negw a1, a1
454454
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
455455
; RV64XTHEADBB-NEXT: or a0, a2, a0
456456
; RV64XTHEADBB-NEXT: ret
@@ -500,7 +500,7 @@ define i32 @rotl_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
500500
; RV64XTHEADBB-LABEL: rotl_32_mask_and_63_and_31:
501501
; RV64XTHEADBB: # %bb.0:
502502
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
503-
; RV64XTHEADBB-NEXT: neg a1, a1
503+
; RV64XTHEADBB-NEXT: negw a1, a1
504504
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
505505
; RV64XTHEADBB-NEXT: or a0, a2, a0
506506
; RV64XTHEADBB-NEXT: ret
@@ -548,7 +548,7 @@ define i32 @rotl_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
548548
; RV64XTHEADBB-LABEL: rotl_32_mask_or_64_or_32:
549549
; RV64XTHEADBB: # %bb.0:
550550
; RV64XTHEADBB-NEXT: sllw a2, a0, a1
551-
; RV64XTHEADBB-NEXT: neg a1, a1
551+
; RV64XTHEADBB-NEXT: negw a1, a1
552552
; RV64XTHEADBB-NEXT: srlw a0, a0, a1
553553
; RV64XTHEADBB-NEXT: or a0, a2, a0
554554
; RV64XTHEADBB-NEXT: ret
@@ -599,7 +599,7 @@ define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {
599599
; RV64XTHEADBB-LABEL: rotr_32_mask:
600600
; RV64XTHEADBB: # %bb.0:
601601
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
602-
; RV64XTHEADBB-NEXT: neg a1, a1
602+
; RV64XTHEADBB-NEXT: negw a1, a1
603603
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
604604
; RV64XTHEADBB-NEXT: or a0, a2, a0
605605
; RV64XTHEADBB-NEXT: ret
@@ -649,7 +649,7 @@ define i32 @rotr_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {
649649
; RV64XTHEADBB-LABEL: rotr_32_mask_and_63_and_31:
650650
; RV64XTHEADBB: # %bb.0:
651651
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
652-
; RV64XTHEADBB-NEXT: neg a1, a1
652+
; RV64XTHEADBB-NEXT: negw a1, a1
653653
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
654654
; RV64XTHEADBB-NEXT: or a0, a2, a0
655655
; RV64XTHEADBB-NEXT: ret
@@ -695,7 +695,7 @@ define i32 @rotr_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
695695
; RV64XTHEADBB-LABEL: rotr_32_mask_or_64_or_32:
696696
; RV64XTHEADBB: # %bb.0:
697697
; RV64XTHEADBB-NEXT: srlw a2, a0, a1
698-
; RV64XTHEADBB-NEXT: neg a1, a1
698+
; RV64XTHEADBB-NEXT: negw a1, a1
699699
; RV64XTHEADBB-NEXT: sllw a0, a0, a1
700700
; RV64XTHEADBB-NEXT: or a0, a2, a0
701701
; RV64XTHEADBB-NEXT: ret
@@ -839,7 +839,7 @@ define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
839839
; RV64XTHEADBB-LABEL: rotl_64_mask:
840840
; RV64XTHEADBB: # %bb.0:
841841
; RV64XTHEADBB-NEXT: sll a2, a0, a1
842-
; RV64XTHEADBB-NEXT: neg a1, a1
842+
; RV64XTHEADBB-NEXT: negw a1, a1
843843
; RV64XTHEADBB-NEXT: srl a0, a0, a1
844844
; RV64XTHEADBB-NEXT: or a0, a2, a0
845845
; RV64XTHEADBB-NEXT: ret
@@ -985,7 +985,7 @@ define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
985985
; RV64XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:
986986
; RV64XTHEADBB: # %bb.0:
987987
; RV64XTHEADBB-NEXT: sll a2, a0, a1
988-
; RV64XTHEADBB-NEXT: neg a1, a1
988+
; RV64XTHEADBB-NEXT: negw a1, a1
989989
; RV64XTHEADBB-NEXT: srl a0, a0, a1
990990
; RV64XTHEADBB-NEXT: or a0, a2, a0
991991
; RV64XTHEADBB-NEXT: ret
@@ -1035,7 +1035,7 @@ define i64 @rotl_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
10351035
; RV64XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:
10361036
; RV64XTHEADBB: # %bb.0:
10371037
; RV64XTHEADBB-NEXT: sll a2, a0, a1
1038-
; RV64XTHEADBB-NEXT: neg a1, a1
1038+
; RV64XTHEADBB-NEXT: negw a1, a1
10391039
; RV64XTHEADBB-NEXT: srl a0, a0, a1
10401040
; RV64XTHEADBB-NEXT: or a0, a2, a0
10411041
; RV64XTHEADBB-NEXT: ret
@@ -1179,7 +1179,7 @@ define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
11791179
; RV64XTHEADBB-LABEL: rotr_64_mask:
11801180
; RV64XTHEADBB: # %bb.0:
11811181
; RV64XTHEADBB-NEXT: srl a2, a0, a1
1182-
; RV64XTHEADBB-NEXT: neg a1, a1
1182+
; RV64XTHEADBB-NEXT: negw a1, a1
11831183
; RV64XTHEADBB-NEXT: sll a0, a0, a1
11841184
; RV64XTHEADBB-NEXT: or a0, a2, a0
11851185
; RV64XTHEADBB-NEXT: ret
@@ -1325,7 +1325,7 @@ define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
13251325
; RV64XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:
13261326
; RV64XTHEADBB: # %bb.0:
13271327
; RV64XTHEADBB-NEXT: srl a2, a0, a1
1328-
; RV64XTHEADBB-NEXT: neg a1, a1
1328+
; RV64XTHEADBB-NEXT: negw a1, a1
13291329
; RV64XTHEADBB-NEXT: sll a0, a0, a1
13301330
; RV64XTHEADBB-NEXT: or a0, a2, a0
13311331
; RV64XTHEADBB-NEXT: ret
@@ -1371,7 +1371,7 @@ define i64 @rotr_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
13711371
; RV64XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:
13721372
; RV64XTHEADBB: # %bb.0:
13731373
; RV64XTHEADBB-NEXT: srl a2, a0, a1
1374-
; RV64XTHEADBB-NEXT: neg a1, a1
1374+
; RV64XTHEADBB-NEXT: negw a1, a1
13751375
; RV64XTHEADBB-NEXT: sll a0, a0, a1
13761376
; RV64XTHEADBB-NEXT: or a0, a2, a0
13771377
; RV64XTHEADBB-NEXT: ret
@@ -1423,19 +1423,18 @@ define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
14231423
;
14241424
; RV32XTHEADBB-LABEL: rotl_32_mask_shared:
14251425
; RV32XTHEADBB: # %bb.0:
1426-
; RV32XTHEADBB-NEXT: andi a3, a2, 31
1427-
; RV32XTHEADBB-NEXT: sll a4, a0, a3
1428-
; RV32XTHEADBB-NEXT: neg a3, a3
1429-
; RV32XTHEADBB-NEXT: srl a0, a0, a3
1430-
; RV32XTHEADBB-NEXT: or a0, a4, a0
1426+
; RV32XTHEADBB-NEXT: sll a3, a0, a2
1427+
; RV32XTHEADBB-NEXT: neg a4, a2
1428+
; RV32XTHEADBB-NEXT: srl a0, a0, a4
1429+
; RV32XTHEADBB-NEXT: or a0, a3, a0
14311430
; RV32XTHEADBB-NEXT: sll a1, a1, a2
14321431
; RV32XTHEADBB-NEXT: add a0, a0, a1
14331432
; RV32XTHEADBB-NEXT: ret
14341433
;
14351434
; RV64XTHEADBB-LABEL: rotl_32_mask_shared:
14361435
; RV64XTHEADBB: # %bb.0:
14371436
; RV64XTHEADBB-NEXT: sllw a3, a0, a2
1438-
; RV64XTHEADBB-NEXT: neg a4, a2
1437+
; RV64XTHEADBB-NEXT: negw a4, a2
14391438
; RV64XTHEADBB-NEXT: srlw a0, a0, a4
14401439
; RV64XTHEADBB-NEXT: or a0, a3, a0
14411440
; RV64XTHEADBB-NEXT: sllw a1, a1, a2
@@ -1600,11 +1599,10 @@ define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
16001599
;
16011600
; RV64XTHEADBB-LABEL: rotl_64_mask_shared:
16021601
; RV64XTHEADBB: # %bb.0:
1603-
; RV64XTHEADBB-NEXT: andi a3, a2, 63
1604-
; RV64XTHEADBB-NEXT: sll a4, a0, a3
1605-
; RV64XTHEADBB-NEXT: neg a3, a3
1606-
; RV64XTHEADBB-NEXT: srl a0, a0, a3
1607-
; RV64XTHEADBB-NEXT: or a0, a4, a0
1602+
; RV64XTHEADBB-NEXT: sll a3, a0, a2
1603+
; RV64XTHEADBB-NEXT: negw a4, a2
1604+
; RV64XTHEADBB-NEXT: srl a0, a0, a4
1605+
; RV64XTHEADBB-NEXT: or a0, a3, a0
16081606
; RV64XTHEADBB-NEXT: sll a1, a1, a2
16091607
; RV64XTHEADBB-NEXT: add a0, a0, a1
16101608
; RV64XTHEADBB-NEXT: ret
@@ -1653,19 +1651,18 @@ define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 sign
16531651
;
16541652
; RV32XTHEADBB-LABEL: rotr_32_mask_shared:
16551653
; RV32XTHEADBB: # %bb.0:
1656-
; RV32XTHEADBB-NEXT: andi a3, a2, 31
1657-
; RV32XTHEADBB-NEXT: srl a4, a0, a3
1658-
; RV32XTHEADBB-NEXT: neg a3, a3
1659-
; RV32XTHEADBB-NEXT: sll a0, a0, a3
1660-
; RV32XTHEADBB-NEXT: or a0, a4, a0
1654+
; RV32XTHEADBB-NEXT: srl a3, a0, a2
1655+
; RV32XTHEADBB-NEXT: neg a4, a2
1656+
; RV32XTHEADBB-NEXT: sll a0, a0, a4
1657+
; RV32XTHEADBB-NEXT: or a0, a3, a0
16611658
; RV32XTHEADBB-NEXT: sll a1, a1, a2
16621659
; RV32XTHEADBB-NEXT: add a0, a0, a1
16631660
; RV32XTHEADBB-NEXT: ret
16641661
;
16651662
; RV64XTHEADBB-LABEL: rotr_32_mask_shared:
16661663
; RV64XTHEADBB: # %bb.0:
16671664
; RV64XTHEADBB-NEXT: srlw a3, a0, a2
1668-
; RV64XTHEADBB-NEXT: neg a4, a2
1665+
; RV64XTHEADBB-NEXT: negw a4, a2
16691666
; RV64XTHEADBB-NEXT: sllw a0, a0, a4
16701667
; RV64XTHEADBB-NEXT: or a0, a3, a0
16711668
; RV64XTHEADBB-NEXT: sllw a1, a1, a2
@@ -1828,11 +1825,10 @@ define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
18281825
;
18291826
; RV64XTHEADBB-LABEL: rotr_64_mask_shared:
18301827
; RV64XTHEADBB: # %bb.0:
1831-
; RV64XTHEADBB-NEXT: andi a3, a2, 63
1832-
; RV64XTHEADBB-NEXT: srl a4, a0, a3
1833-
; RV64XTHEADBB-NEXT: neg a3, a3
1834-
; RV64XTHEADBB-NEXT: sll a0, a0, a3
1835-
; RV64XTHEADBB-NEXT: or a0, a4, a0
1828+
; RV64XTHEADBB-NEXT: srl a3, a0, a2
1829+
; RV64XTHEADBB-NEXT: negw a4, a2
1830+
; RV64XTHEADBB-NEXT: sll a0, a0, a4
1831+
; RV64XTHEADBB-NEXT: or a0, a3, a0
18361832
; RV64XTHEADBB-NEXT: sll a1, a1, a2
18371833
; RV64XTHEADBB-NEXT: add a0, a0, a1
18381834
; RV64XTHEADBB-NEXT: ret
@@ -1885,7 +1881,6 @@ define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
18851881
;
18861882
; RV32XTHEADBB-LABEL: rotl_32_mask_multiple:
18871883
; RV32XTHEADBB: # %bb.0:
1888-
; RV32XTHEADBB-NEXT: andi a2, a2, 31
18891884
; RV32XTHEADBB-NEXT: sll a3, a0, a2
18901885
; RV32XTHEADBB-NEXT: neg a4, a2
18911886
; RV32XTHEADBB-NEXT: srl a0, a0, a4
@@ -1898,9 +1893,8 @@ define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
18981893
;
18991894
; RV64XTHEADBB-LABEL: rotl_32_mask_multiple:
19001895
; RV64XTHEADBB: # %bb.0:
1901-
; RV64XTHEADBB-NEXT: andi a2, a2, 31
19021896
; RV64XTHEADBB-NEXT: sllw a3, a0, a2
1903-
; RV64XTHEADBB-NEXT: neg a4, a2
1897+
; RV64XTHEADBB-NEXT: negw a4, a2
19041898
; RV64XTHEADBB-NEXT: srlw a0, a0, a4
19051899
; RV64XTHEADBB-NEXT: or a0, a3, a0
19061900
; RV64XTHEADBB-NEXT: sllw a2, a1, a2
@@ -2071,9 +2065,8 @@ define i64 @rotl_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
20712065
;
20722066
; RV64XTHEADBB-LABEL: rotl_64_mask_multiple:
20732067
; RV64XTHEADBB: # %bb.0:
2074-
; RV64XTHEADBB-NEXT: andi a2, a2, 63
20752068
; RV64XTHEADBB-NEXT: sll a3, a0, a2
2076-
; RV64XTHEADBB-NEXT: neg a4, a2
2069+
; RV64XTHEADBB-NEXT: negw a4, a2
20772070
; RV64XTHEADBB-NEXT: srl a0, a0, a4
20782071
; RV64XTHEADBB-NEXT: or a0, a3, a0
20792072
; RV64XTHEADBB-NEXT: sll a2, a1, a2
@@ -2129,7 +2122,6 @@ define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
21292122
;
21302123
; RV32XTHEADBB-LABEL: rotr_32_mask_multiple:
21312124
; RV32XTHEADBB: # %bb.0:
2132-
; RV32XTHEADBB-NEXT: andi a2, a2, 31
21332125
; RV32XTHEADBB-NEXT: srl a3, a0, a2
21342126
; RV32XTHEADBB-NEXT: neg a4, a2
21352127
; RV32XTHEADBB-NEXT: sll a0, a0, a4
@@ -2142,9 +2134,8 @@ define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 si
21422134
;
21432135
; RV64XTHEADBB-LABEL: rotr_32_mask_multiple:
21442136
; RV64XTHEADBB: # %bb.0:
2145-
; RV64XTHEADBB-NEXT: andi a2, a2, 31
21462137
; RV64XTHEADBB-NEXT: srlw a3, a0, a2
2147-
; RV64XTHEADBB-NEXT: neg a4, a2
2138+
; RV64XTHEADBB-NEXT: negw a4, a2
21482139
; RV64XTHEADBB-NEXT: sllw a0, a0, a4
21492140
; RV64XTHEADBB-NEXT: or a0, a3, a0
21502141
; RV64XTHEADBB-NEXT: srlw a2, a1, a2
@@ -2313,9 +2304,8 @@ define i64 @rotr_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
23132304
;
23142305
; RV64XTHEADBB-LABEL: rotr_64_mask_multiple:
23152306
; RV64XTHEADBB: # %bb.0:
2316-
; RV64XTHEADBB-NEXT: andi a2, a2, 63
23172307
; RV64XTHEADBB-NEXT: srl a3, a0, a2
2318-
; RV64XTHEADBB-NEXT: neg a4, a2
2308+
; RV64XTHEADBB-NEXT: negw a4, a2
23192309
; RV64XTHEADBB-NEXT: sll a0, a0, a4
23202310
; RV64XTHEADBB-NEXT: or a0, a3, a0
23212311
; RV64XTHEADBB-NEXT: srl a2, a1, a2
@@ -2467,7 +2457,7 @@ define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind {
24672457
; RV64XTHEADBB-LABEL: rotl_64_zext:
24682458
; RV64XTHEADBB: # %bb.0:
24692459
; RV64XTHEADBB-NEXT: sll a2, a0, a1
2470-
; RV64XTHEADBB-NEXT: neg a1, a1
2460+
; RV64XTHEADBB-NEXT: negw a1, a1
24712461
; RV64XTHEADBB-NEXT: srl a0, a0, a1
24722462
; RV64XTHEADBB-NEXT: or a0, a2, a0
24732463
; RV64XTHEADBB-NEXT: ret
@@ -2617,7 +2607,7 @@ define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind {
26172607
; RV64XTHEADBB-LABEL: rotr_64_zext:
26182608
; RV64XTHEADBB: # %bb.0:
26192609
; RV64XTHEADBB-NEXT: srl a2, a0, a1
2620-
; RV64XTHEADBB-NEXT: neg a1, a1
2610+
; RV64XTHEADBB-NEXT: negw a1, a1
26212611
; RV64XTHEADBB-NEXT: sll a0, a0, a1
26222612
; RV64XTHEADBB-NEXT: or a0, a2, a0
26232613
; RV64XTHEADBB-NEXT: ret

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