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[NFC][MC] MCRegister API typing.
Mostly LiveIntervals, with their effects (users). Differential Revision: https://reviews.llvm.org/D89018
1 parent 19119dd commit 4cfc402

12 files changed

+39
-33
lines changed

‎llvm/include/llvm/CodeGen/LiveIntervals.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -431,7 +431,7 @@ class VirtRegMap;
431431
/// Remove value numbers and related live segments starting at position
432432
/// \p Pos that are part of any liverange of physical register \p Reg or one
433433
/// of its subregisters.
434-
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
434+
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos);
435435

436436
/// Remove value number and related live segments of \p LI and its subranges
437437
/// that start at position \p Pos.

‎llvm/include/llvm/CodeGen/VirtRegMap.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,9 +98,9 @@ class TargetInstrInfo;
9898

9999
/// returns the physical register mapped to the specified
100100
/// virtual register
101-
Register getPhys(Register virtReg) const {
101+
MCRegister getPhys(Register virtReg) const {
102102
assert(virtReg.isVirtual());
103-
return Virt2PhysMap[virtReg.id()];
103+
return MCRegister::from(Virt2PhysMap[virtReg.id()]);
104104
}
105105

106106
/// creates a mapping for the specified virtual register to

‎llvm/lib/CodeGen/InlineSpiller.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -881,7 +881,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
881881
// FoldMI does not define this physreg. Remove the LI segment.
882882
assert(MO->isDead() && "Cannot fold physreg def");
883883
SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
884-
LIS.removePhysRegDefAt(Reg, Idx);
884+
LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
885885
}
886886

887887
int FI;

‎llvm/lib/CodeGen/LiveIntervals.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1037,7 +1037,8 @@ class LiveIntervals::HMEditor {
10371037

10381038
// For physregs, only update the regunits that actually have a
10391039
// precomputed live range.
1040-
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1040+
for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
1041+
++Units)
10411042
if (LiveRange *LR = getRegUnitLI(*Units))
10421043
updateRange(*LR, *Units, LaneBitmask::getNone());
10431044
}
@@ -1683,7 +1684,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
16831684
}
16841685
}
16851686

1686-
void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
1687+
void LiveIntervals::removePhysRegDefAt(MCRegister Reg, SlotIndex Pos) {
16871688
for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
16881689
if (LiveRange *LR = getCachedRegUnit(*Unit))
16891690
if (VNInfo *VNI = LR->getVNInfoAt(Pos))

‎llvm/lib/CodeGen/LiveRangeEdit.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -316,7 +316,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
316316
if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
317317
ReadsPhysRegs = true;
318318
else if (MOI->isDef())
319-
LIS.removePhysRegDefAt(Reg, Idx);
319+
LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
320320
continue;
321321
}
322322
LiveInterval &LI = LIS.getInterval(Reg);

‎llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2866,7 +2866,7 @@ void RAGreedy::collectHintInfo(unsigned Reg, HintsInfo &Out) {
28662866
// Get the current assignment.
28672867
Register OtherPhysReg = Register::isPhysicalRegister(OtherReg)
28682868
? OtherReg
2869-
: VRM->getPhys(OtherReg);
2869+
: Register(VRM->getPhys(OtherReg));
28702870
// Push the collected information.
28712871
Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
28722872
OtherPhysReg));

‎llvm/lib/CodeGen/RegisterCoalescer.cpp

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ namespace {
173173
SmallVector<MachineInstr*, 8> DeadDefs;
174174

175175
/// Virtual registers to be considered for register class inflation.
176-
SmallVector<unsigned, 8> InflateRegs;
176+
SmallVector<Register, 8> InflateRegs;
177177

178178
/// The collection of live intervals which should have been updated
179179
/// immediately after rematerialiation but delayed until
@@ -285,7 +285,7 @@ namespace {
285285
/// number if it is not zero. If DstReg is a physical register and the
286286
/// existing subregister number of the def / use being updated is not zero,
287287
/// make sure to set it to the correct physical subregister.
288-
void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
288+
void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx);
289289

290290
/// If the given machine operand reads only undefined lanes add an undef
291291
/// flag.
@@ -1246,9 +1246,9 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
12461246
MachineInstr *CopyMI,
12471247
bool &IsDefCopy) {
12481248
IsDefCopy = false;
1249-
unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
1249+
Register SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
12501250
unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
1251-
unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1251+
Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
12521252
unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
12531253
if (Register::isPhysicalRegister(SrcReg))
12541254
return false;
@@ -1700,7 +1700,7 @@ void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
17001700
}
17011701
}
17021702

1703-
void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg, unsigned DstReg,
1703+
void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
17041704
unsigned SubIdx) {
17051705
bool DstIsPhys = Register::isPhysicalRegister(DstReg);
17061706
LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
@@ -1942,7 +1942,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
19421942
if (Changed) {
19431943
deleteInstr(CopyMI);
19441944
if (Shrink) {
1945-
unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1945+
Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
19461946
LiveInterval &DstLI = LIS->getInterval(DstReg);
19471947
shrinkToUses(&DstLI);
19481948
LLVM_DEBUG(dbgs() << "\t\tshrunk: " << DstLI << '\n');
@@ -2034,8 +2034,8 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
20342034
}
20352035

20362036
bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
2037-
unsigned DstReg = CP.getDstReg();
2038-
unsigned SrcReg = CP.getSrcReg();
2037+
Register DstReg = CP.getDstReg();
2038+
Register SrcReg = CP.getSrcReg();
20392039
assert(CP.isPhys() && "Must be a physreg copy");
20402040
assert(MRI->isReserved(DstReg) && "Not a reserved register");
20412041
LiveInterval &RHS = LIS->getInterval(SrcReg);
@@ -2132,7 +2132,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
21322132
LLVM_DEBUG(dbgs() << "\t\tRemoving phys reg def of "
21332133
<< printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n");
21342134

2135-
LIS->removePhysRegDefAt(DstReg, CopyRegIdx);
2135+
LIS->removePhysRegDefAt(DstReg.asMCReg(), CopyRegIdx);
21362136
// Create a new dead def at the new def location.
21372137
for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
21382138
LiveRange &LR = LIS->getRegUnit(*UI);
@@ -2393,14 +2393,15 @@ class JoinVals {
23932393
bool isPrunedValue(unsigned ValNo, JoinVals &Other);
23942394

23952395
public:
2396-
JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask,
2397-
SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp,
2396+
JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask,
2397+
SmallVectorImpl<VNInfo *> &newVNInfo, const CoalescerPair &cp,
23982398
LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
23992399
bool TrackSubRegLiveness)
2400-
: LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
2401-
SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
2402-
NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
2403-
TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums()) {}
2400+
: LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
2401+
SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
2402+
NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
2403+
TRI(TRI), Assignments(LR.getNumValNums(), -1),
2404+
Vals(LR.getNumValNums()) {}
24042405

24052406
/// Analyze defs in LR and compute a value mapping in NewVNInfo.
24062407
/// Returns false if any conflicts were impossible to resolve.

‎llvm/lib/CodeGen/RegisterCoalescer.h

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,8 @@
1414
#ifndef LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
1515
#define LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
1616

17+
#include "llvm/CodeGen/Register.h"
18+
1719
namespace llvm {
1820

1921
class MachineInstr;
@@ -28,10 +30,10 @@ class TargetRegisterInfo;
2830

2931
/// The register that will be left after coalescing. It can be a
3032
/// virtual or physical register.
31-
unsigned DstReg = 0;
33+
Register DstReg;
3234

3335
/// The virtual register that will be coalesced into dstReg.
34-
unsigned SrcReg = 0;
36+
Register SrcReg;
3537

3638
/// The sub-register index of the old DstReg in the new coalesced register.
3739
unsigned DstIdx = 0;
@@ -92,10 +94,10 @@ class TargetRegisterInfo;
9294

9395
/// Return the register (virtual or physical) that will remain
9496
/// after coalescing.
95-
unsigned getDstReg() const { return DstReg; }
97+
Register getDstReg() const { return DstReg; }
9698

9799
/// Return the virtual register that will be coalesced away.
98-
unsigned getSrcReg() const { return SrcReg; }
100+
Register getSrcReg() const { return SrcReg; }
99101

100102
/// Return the subregister index that DstReg will be coalesced into, or 0.
101103
unsigned getDstIdx() const { return DstIdx; }

‎llvm/lib/CodeGen/VirtRegMap.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ bool VirtRegMap::hasPreferredPhys(Register VirtReg) {
104104
return false;
105105
if (Hint.isVirtual())
106106
Hint = getPhys(Hint);
107-
return getPhys(VirtReg) == Hint;
107+
return Register(getPhys(VirtReg)) == Hint;
108108
}
109109

110110
bool VirtRegMap::hasKnownPreference(Register VirtReg) {

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1196,7 +1196,7 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
11961196
if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
11971197
Register Reg = MI.getOperand(I).getReg();
11981198
Register PhysReg = Register::isVirtualRegister(Reg)
1199-
? (VRM ? VRM->getPhys(Reg) : Register())
1199+
? (VRM ? Register(VRM->getPhys(Reg)) : Register())
12001200
: Reg;
12011201
if (!PhysReg ||
12021202
!(SystemZ::FP32BitRegClass.contains(PhysReg) ||
@@ -1242,7 +1242,8 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
12421242
else {
12431243
Register DstReg = MI.getOperand(0).getReg();
12441244
Register DstPhys =
1245-
(Register::isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg);
1245+
(Register::isVirtualRegister(DstReg) ? Register(VRM->getPhys(DstReg))
1246+
: DstReg);
12461247
Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
12471248
: ((OpNum == 1 && MI.isCommutable())
12481249
? MI.getOperand(2).getReg()

‎llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -109,8 +109,9 @@ bool SystemZRegisterInfo::getRegAllocationHints(
109109

110110
auto tryAddHint = [&](const MachineOperand *MO) -> void {
111111
Register Reg = MO->getReg();
112-
Register PhysReg =
113-
Register::isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
112+
Register PhysReg = Register::isPhysicalRegister(Reg)
113+
? Reg
114+
: Register(VRM->getPhys(Reg));
114115
if (PhysReg) {
115116
if (MO->getSubReg())
116117
PhysReg = getSubReg(PhysReg, MO->getSubReg());

‎llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -595,7 +595,7 @@ static MachineInstr *rematerializeCheapDef(
595595
if (IsDead) {
596596
LLVM_DEBUG(dbgs() << " - Deleting original\n");
597597
SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
598-
LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx);
598+
LIS.removePhysRegDefAt(MCRegister::from(WebAssembly::ARGUMENTS), Idx);
599599
LIS.removeInterval(Reg);
600600
LIS.RemoveMachineInstrFromMaps(Def);
601601
Def.eraseFromParent();

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