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[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
Add a comment when there is a shifted value, add x9, x0, #291, lsl #12 ; =1191936 but not when the immediate value is unshifted, subs x9, x0, #256 ; =256 when the comment adds nothing additional to the reader. Differential Revision: https://reviews.llvm.org/D107196 (cherry picked from commit 0d8cd4e)
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‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -962,11 +962,11 @@ void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
962962
unsigned Shift =
963963
AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
964964
O << '#' << formatImm(Val);
965-
if (Shift != 0)
965+
if (Shift != 0) {
966966
printShifter(MI, OpNum + 1, STI, O);
967-
968-
if (CommentStream)
969-
*CommentStream << '=' << formatImm(Val << Shift) << '\n';
967+
if (CommentStream)
968+
*CommentStream << '=' << formatImm(Val << Shift) << '\n';
969+
}
970970
} else {
971971
assert(MO.isExpr() && "Unexpected operand type!");
972972
MO.getExpr()->print(O, &MAI);

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

+16-17
Original file line numberDiff line numberDiff line change
@@ -325,7 +325,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
325325
;
326326
; CHECK-NOLSE-O0-LABEL: fetch_and_nand:
327327
; CHECK-NOLSE-O0: ; %bb.0:
328-
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
328+
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
329329
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
330330
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
331331
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
@@ -355,7 +355,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
355355
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB6_1
356356
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
357357
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
358-
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
358+
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
359359
; CHECK-NOLSE-O0-NEXT: ret
360360
;
361361
; CHECK-LSE-O1-LABEL: fetch_and_nand:
@@ -373,7 +373,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
373373
;
374374
; CHECK-LSE-O0-LABEL: fetch_and_nand:
375375
; CHECK-LSE-O0: ; %bb.0:
376-
; CHECK-LSE-O0-NEXT: sub sp, sp, #32 ; =32
376+
; CHECK-LSE-O0-NEXT: sub sp, sp, #32
377377
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
378378
; CHECK-LSE-O0-NEXT: ldr w8, [x0]
379379
; CHECK-LSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
@@ -392,7 +392,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
392392
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB6_1
393393
; CHECK-LSE-O0-NEXT: ; %bb.2: ; %atomicrmw.end
394394
; CHECK-LSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
395-
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32
395+
; CHECK-LSE-O0-NEXT: add sp, sp, #32
396396
; CHECK-LSE-O0-NEXT: ret
397397
%val = atomicrmw nand i32* %p, i32 7 release
398398
ret i32 %val
@@ -414,7 +414,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
414414
;
415415
; CHECK-NOLSE-O0-LABEL: fetch_and_nand_64:
416416
; CHECK-NOLSE-O0: ; %bb.0:
417-
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
417+
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
418418
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
419419
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
420420
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
@@ -444,7 +444,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
444444
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB7_1
445445
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
446446
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
447-
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
447+
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
448448
; CHECK-NOLSE-O0-NEXT: ret
449449
;
450450
; CHECK-LSE-O1-LABEL: fetch_and_nand_64:
@@ -462,7 +462,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
462462
;
463463
; CHECK-LSE-O0-LABEL: fetch_and_nand_64:
464464
; CHECK-LSE-O0: ; %bb.0:
465-
; CHECK-LSE-O0-NEXT: sub sp, sp, #32 ; =32
465+
; CHECK-LSE-O0-NEXT: sub sp, sp, #32
466466
; CHECK-LSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
467467
; CHECK-LSE-O0-NEXT: ldr x8, [x0]
468468
; CHECK-LSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
@@ -481,7 +481,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 {
481481
; CHECK-LSE-O0-NEXT: tbz w8, #0, LBB7_1
482482
; CHECK-LSE-O0-NEXT: ; %bb.2: ; %atomicrmw.end
483483
; CHECK-LSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
484-
; CHECK-LSE-O0-NEXT: add sp, sp, #32 ; =32
484+
; CHECK-LSE-O0-NEXT: add sp, sp, #32
485485
; CHECK-LSE-O0-NEXT: ret
486486
%val = atomicrmw nand i64* %p, i64 7 acq_rel
487487
ret i64 %val
@@ -503,7 +503,7 @@ define i32 @fetch_and_or(i32* %p) #0 {
503503
;
504504
; CHECK-NOLSE-O0-LABEL: fetch_and_or:
505505
; CHECK-NOLSE-O0: ; %bb.0:
506-
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
506+
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
507507
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
508508
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
509509
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
@@ -533,7 +533,7 @@ define i32 @fetch_and_or(i32* %p) #0 {
533533
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB8_1
534534
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
535535
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
536-
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
536+
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
537537
; CHECK-NOLSE-O0-NEXT: ret
538538
;
539539
; CHECK-LSE-O1-LABEL: fetch_and_or:
@@ -566,7 +566,7 @@ define i64 @fetch_and_or_64(i64* %p) #0 {
566566
;
567567
; CHECK-NOLSE-O0-LABEL: fetch_and_or_64:
568568
; CHECK-NOLSE-O0: ; %bb.0:
569-
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32 ; =32
569+
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
570570
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
571571
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
572572
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Folded Spill
@@ -595,7 +595,7 @@ define i64 @fetch_and_or_64(i64* %p) #0 {
595595
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB9_1
596596
; CHECK-NOLSE-O0-NEXT: ; %bb.5: ; %atomicrmw.end
597597
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp, #8] ; 8-byte Folded Reload
598-
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32 ; =32
598+
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
599599
; CHECK-NOLSE-O0-NEXT: ret
600600
;
601601
; CHECK-LSE-O1-LABEL: fetch_and_or_64:
@@ -709,7 +709,7 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
709709
; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw
710710
; CHECK-NOLSE-O0-NEXT: ldrb w8, [x8]
711711
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb
712-
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256 ; =256
712+
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256
713713
; CHECK-NOLSE-O0-NEXT: ldrb w9, [x9]
714714
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxtb
715715
; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
@@ -735,7 +735,7 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
735735
; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw
736736
; CHECK-LSE-O0-NEXT: ldrb w8, [x8]
737737
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb
738-
; CHECK-LSE-O0-NEXT: subs x9, x0, #256 ; =256
738+
; CHECK-LSE-O0-NEXT: subs x9, x0, #256
739739
; CHECK-LSE-O0-NEXT: ldrb w9, [x9]
740740
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxtb
741741
; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
@@ -779,7 +779,7 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
779779
; CHECK-NOLSE-O0-NEXT: add x8, x0, w1, sxtw #1
780780
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x8]
781781
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth
782-
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256 ; =256
782+
; CHECK-NOLSE-O0-NEXT: subs x9, x0, #256
783783
; CHECK-NOLSE-O0-NEXT: ldrh w9, [x9]
784784
; CHECK-NOLSE-O0-NEXT: add w8, w8, w9, uxth
785785
; CHECK-NOLSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
@@ -805,7 +805,7 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
805805
; CHECK-LSE-O0-NEXT: add x8, x0, w1, sxtw #1
806806
; CHECK-LSE-O0-NEXT: ldrh w8, [x8]
807807
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth
808-
; CHECK-LSE-O0-NEXT: subs x9, x0, #256 ; =256
808+
; CHECK-LSE-O0-NEXT: subs x9, x0, #256
809809
; CHECK-LSE-O0-NEXT: ldrh w9, [x9]
810810
; CHECK-LSE-O0-NEXT: add w8, w8, w9, uxth
811811
; CHECK-LSE-O0-NEXT: add x9, x0, #291, lsl #12 ; =1191936
@@ -1323,5 +1323,4 @@ define void @store_trunc(i32 %val, i8* %p8, i16* %p16) {
13231323
ret void
13241324
}
13251325

1326-
13271326
attributes #0 = { nounwind }

‎llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll

+5-5
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,15 @@ declare void @byval_i32(i32* byval(i32) %ptr)
66
define void @call_byval_i32(i32* %incoming) {
77
; CHECK-LABEL: call_byval_i32:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: sub sp, sp, #32 // =32
9+
; CHECK-NEXT: sub sp, sp, #32
1010
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
1111
; CHECK-NEXT: .cfi_def_cfa_offset 32
1212
; CHECK-NEXT: .cfi_offset w30, -16
1313
; CHECK-NEXT: ldr w8, [x0]
1414
; CHECK-NEXT: str w8, [sp]
1515
; CHECK-NEXT: bl byval_i32
1616
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
17-
; CHECK-NEXT: add sp, sp, #32 // =32
17+
; CHECK-NEXT: add sp, sp, #32
1818
; CHECK-NEXT: ret
1919
call void @byval_i32(i32* byval(i32) %incoming)
2020
ret void
@@ -25,10 +25,10 @@ declare void @byval_a64i32([64 x i32]* byval([64 x i32]) %ptr)
2525
define void @call_byval_a64i32([64 x i32]* %incoming) {
2626
; CHECK-LABEL: call_byval_a64i32:
2727
; CHECK: // %bb.0:
28-
; CHECK-NEXT: sub sp, sp, #288 // =288
28+
; CHECK-NEXT: sub sp, sp, #288
2929
; CHECK-NEXT: stp x29, x30, [sp, #256] // 16-byte Folded Spill
3030
; CHECK-NEXT: str x28, [sp, #272] // 8-byte Folded Spill
31-
; CHECK-NEXT: add x29, sp, #256 // =256
31+
; CHECK-NEXT: add x29, sp, #256
3232
; CHECK-NEXT: .cfi_def_cfa w29, 32
3333
; CHECK-NEXT: .cfi_offset w28, -16
3434
; CHECK-NEXT: .cfi_offset w30, -24
@@ -68,7 +68,7 @@ define void @call_byval_a64i32([64 x i32]* %incoming) {
6868
; CHECK-NEXT: bl byval_a64i32
6969
; CHECK-NEXT: ldr x28, [sp, #272] // 8-byte Folded Reload
7070
; CHECK-NEXT: ldp x29, x30, [sp, #256] // 16-byte Folded Reload
71-
; CHECK-NEXT: add sp, sp, #288 // =288
71+
; CHECK-NEXT: add sp, sp, #288
7272
; CHECK-NEXT: ret
7373
call void @byval_a64i32([64 x i32]* byval([64 x i32]) %incoming)
7474
ret void

‎llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll

+6-6
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ declare void @puts(i8*)
3030
define i32 @test_musttail_variadic_spill(i32 %arg0, ...) {
3131
; CHECK-LABEL: test_musttail_variadic_spill:
3232
; CHECK: ; %bb.0:
33-
; CHECK-NEXT: sub sp, sp, #224 ; =224
33+
; CHECK-NEXT: sub sp, sp, #224
3434
; CHECK-NEXT: stp x28, x27, [sp, #128] ; 16-byte Folded Spill
3535
; CHECK-NEXT: stp x26, x25, [sp, #144] ; 16-byte Folded Spill
3636
; CHECK-NEXT: stp x24, x23, [sp, #160] ; 16-byte Folded Spill
@@ -87,7 +87,7 @@ define i32 @test_musttail_variadic_spill(i32 %arg0, ...) {
8787
; CHECK-NEXT: ldp x24, x23, [sp, #160] ; 16-byte Folded Reload
8888
; CHECK-NEXT: ldp x26, x25, [sp, #144] ; 16-byte Folded Reload
8989
; CHECK-NEXT: ldp x28, x27, [sp, #128] ; 16-byte Folded Reload
90-
; CHECK-NEXT: add sp, sp, #224 ; =224
90+
; CHECK-NEXT: add sp, sp, #224
9191
; CHECK-NEXT: b _musttail_variadic_callee
9292
; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
9393
call void @puts(i8* getelementptr ([4 x i8], [4 x i8]* @asdf, i32 0, i32 0))
@@ -102,7 +102,7 @@ declare void(i8*, ...)* @get_f(i8* %this)
102102
define void @f_thunk(i8* %this, ...) {
103103
; CHECK-LABEL: f_thunk:
104104
; CHECK: ; %bb.0:
105-
; CHECK-NEXT: sub sp, sp, #256 ; =256
105+
; CHECK-NEXT: sub sp, sp, #256
106106
; CHECK-NEXT: stp x28, x27, [sp, #160] ; 16-byte Folded Spill
107107
; CHECK-NEXT: stp x26, x25, [sp, #176] ; 16-byte Folded Spill
108108
; CHECK-NEXT: stp x24, x23, [sp, #192] ; 16-byte Folded Spill
@@ -123,8 +123,8 @@ define void @f_thunk(i8* %this, ...) {
123123
; CHECK-NEXT: .cfi_offset w27, -88
124124
; CHECK-NEXT: .cfi_offset w28, -96
125125
; CHECK-NEXT: mov x27, x8
126-
; CHECK-NEXT: add x8, sp, #128 ; =128
127-
; CHECK-NEXT: add x9, sp, #256 ; =256
126+
; CHECK-NEXT: add x8, sp, #128
127+
; CHECK-NEXT: add x9, sp, #256
128128
; CHECK-NEXT: mov x19, x0
129129
; CHECK-NEXT: mov x20, x1
130130
; CHECK-NEXT: mov x21, x2
@@ -159,7 +159,7 @@ define void @f_thunk(i8* %this, ...) {
159159
; CHECK-NEXT: ldp x24, x23, [sp, #192] ; 16-byte Folded Reload
160160
; CHECK-NEXT: ldp x26, x25, [sp, #176] ; 16-byte Folded Reload
161161
; CHECK-NEXT: ldp x28, x27, [sp, #160] ; 16-byte Folded Reload
162-
; CHECK-NEXT: add sp, sp, #256 ; =256
162+
; CHECK-NEXT: add sp, sp, #256
163163
; CHECK-NEXT: br x9
164164
%ap = alloca [4 x i8*], align 16
165165
%ap_i8 = bitcast [4 x i8*]* %ap to i8*

‎llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -67,12 +67,12 @@ define <2 x i32> @freeze_ivec() {
6767
define i8* @freeze_ptr() {
6868
; CHECK-LABEL: freeze_ptr:
6969
; CHECK: // %bb.0:
70-
; CHECK-NEXT: add x0, x8, #4 // =4
70+
; CHECK-NEXT: add x0, x8, #4
7171
; CHECK-NEXT: ret
7272
;
7373
; GISEL-LABEL: freeze_ptr:
7474
; GISEL: // %bb.0:
75-
; GISEL-NEXT: add x0, x8, #4 // =4
75+
; GISEL-NEXT: add x0, x8, #4
7676
; GISEL-NEXT: ret
7777
%y1 = freeze i8* undef
7878
%t1 = getelementptr i8, i8* %y1, i64 4

‎llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -154,14 +154,14 @@ entry:
154154
}
155155
; CHECK-LABEL: novla_nodynamicrealign_nocall
156156
; Check that space is reserved for one local variable on the stack.
157-
; CHECK: sub sp, sp, #16 // =16
157+
; CHECK: sub sp, sp, #16
158158
; Check correct access to arguments passed on the stack, through stack pointer
159159
; CHECK: ldr d[[DARG:[0-9]+]], [sp, #40]
160160
; CHECK: ldr w[[IARG:[0-9]+]], [sp, #24]
161161
; Check correct access to local variable on the stack, through stack pointer
162162
; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12]
163163
; Check epilogue:
164-
; CHECK: add sp, sp, #16 // =16
164+
; CHECK: add sp, sp, #16
165165
; CHECK: ret
166166

167167

@@ -394,7 +394,7 @@ entry:
394394
; bytes & the base pointer (x19) gets initialized to
395395
; this 128-byte aligned area for local variables &
396396
; spill slots
397-
; CHECK: sub x9, sp, #80 // =80
397+
; CHECK: sub x9, sp, #80
398398
; CHECK: and sp, x9, #0xffffffffffffff80
399399
; CHECK: mov x19, sp
400400
; Check correctness of cfi pseudo-instructions
@@ -688,7 +688,7 @@ bb1:
688688
; CHECK-LABEL: realign_conditional2
689689
; Extra realignment in the prologue (performance issue).
690690
; CHECK: tbz {{.*}} .[[LABEL:.*]]
691-
; CHECK: sub x9, sp, #32 // =32
691+
; CHECK: sub x9, sp, #32
692692
; CHECK: and sp, x9, #0xffffffffffffffe0
693693
; CHECK: mov x19, sp
694694
; Stack is realigned in a non-entry BB.

‎llvm/test/CodeGen/AArch64/aarch64-load-ext.ll

+4-4
Original file line numberDiff line numberDiff line change
@@ -23,15 +23,15 @@ define <2 x i16> @test1(<2 x i16>* %v2i16_ptr) {
2323
; CHECK-LE-LABEL: test1:
2424
; CHECK-LE: // %bb.0:
2525
; CHECK-LE-NEXT: ld1 { v0.h }[0], [x0]
26-
; CHECK-LE-NEXT: add x8, x0, #2 // =2
26+
; CHECK-LE-NEXT: add x8, x0, #2
2727
; CHECK-LE-NEXT: ld1 { v0.h }[2], [x8]
2828
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
2929
; CHECK-LE-NEXT: ret
3030
;
3131
; CHECK-BE-LABEL: test1:
3232
; CHECK-BE: // %bb.0:
3333
; CHECK-BE-NEXT: ld1 { v0.h }[0], [x0]
34-
; CHECK-BE-NEXT: add x8, x0, #2 // =2
34+
; CHECK-BE-NEXT: add x8, x0, #2
3535
; CHECK-BE-NEXT: ld1 { v0.h }[2], [x8]
3636
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
3737
; CHECK-BE-NEXT: ret
@@ -67,15 +67,15 @@ define <2 x i8> @test3(<2 x i8>* %v2i8_ptr) {
6767
; CHECK-LE-LABEL: test3:
6868
; CHECK-LE: // %bb.0:
6969
; CHECK-LE-NEXT: ld1 { v0.b }[0], [x0]
70-
; CHECK-LE-NEXT: add x8, x0, #1 // =1
70+
; CHECK-LE-NEXT: add x8, x0, #1
7171
; CHECK-LE-NEXT: ld1 { v0.b }[4], [x8]
7272
; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
7373
; CHECK-LE-NEXT: ret
7474
;
7575
; CHECK-BE-LABEL: test3:
7676
; CHECK-BE: // %bb.0:
7777
; CHECK-BE-NEXT: ld1 { v0.b }[0], [x0]
78-
; CHECK-BE-NEXT: add x8, x0, #1 // =1
78+
; CHECK-BE-NEXT: add x8, x0, #1
7979
; CHECK-BE-NEXT: ld1 { v0.b }[4], [x8]
8080
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
8181
; CHECK-BE-NEXT: ret

‎llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll

+6-6
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ define void @matrix_mul_unsigned(i32 %N, i32* nocapture %C, i16* nocapture reado
1313
; CHECK-NEXT: add x9, x2, w0, uxtw #1
1414
; CHECK-NEXT: ldp d1, d2, [x9]
1515
; CHECK-NEXT: add x9, x1, w0, uxtw #2
16-
; CHECK-NEXT: subs x8, x8, #8 // =8
17-
; CHECK-NEXT: add w0, w0, #8 // =8
16+
; CHECK-NEXT: subs x8, x8, #8
17+
; CHECK-NEXT: add w0, w0, #8
1818
; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
1919
; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h
2020
; CHECK-NEXT: stp q1, q2, [x9]
@@ -77,8 +77,8 @@ define void @matrix_mul_signed(i32 %N, i32* nocapture %C, i16* nocapture readonl
7777
; CHECK-NEXT: add x9, x2, w0, sxtw #1
7878
; CHECK-NEXT: ldp d1, d2, [x9]
7979
; CHECK-NEXT: add x9, x1, w0, sxtw #2
80-
; CHECK-NEXT: subs x8, x8, #8 // =8
81-
; CHECK-NEXT: add w0, w0, #8 // =8
80+
; CHECK-NEXT: subs x8, x8, #8
81+
; CHECK-NEXT: add w0, w0, #8
8282
; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
8383
; CHECK-NEXT: smull v2.4s, v0.4h, v2.4h
8484
; CHECK-NEXT: stp q1, q2, [x9]
@@ -141,11 +141,11 @@ define void @matrix_mul_double_shuffle(i32 %N, i32* nocapture %C, i16* nocapture
141141
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
142142
; CHECK-NEXT: ldrh w9, [x2], #16
143143
; CHECK-NEXT: mov w10, w0
144-
; CHECK-NEXT: subs x8, x8, #8 // =8
144+
; CHECK-NEXT: subs x8, x8, #8
145145
; CHECK-NEXT: lsl x10, x10, #2
146146
; CHECK-NEXT: dup v1.4h, w9
147147
; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
148-
; CHECK-NEXT: add w0, w0, #8 // =8
148+
; CHECK-NEXT: add w0, w0, #8
149149
; CHECK-NEXT: str q1, [x1, x10]
150150
; CHECK-NEXT: b.ne .LBB2_1
151151
; CHECK-NEXT: // %bb.2: // %for.end12

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