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Merge commit 'c7ee3048da28' from apple/master into swift/master-next
2 parents 0343de7 + c7ee304 commit 72820bc

13 files changed

+133
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lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -64,11 +64,6 @@ template <class T> class SmallVectorImpl;
6464

6565
using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
6666

67-
struct DestSourcePair {
68-
const MachineOperand &Destination;
69-
const MachineOperand &Source;
70-
};
71-
7267
//---------------------------------------------------------------------------
7368
///
7469
/// TargetInstrInfo - Interface to description of machine instruction set
@@ -923,36 +918,41 @@ class TargetInstrInfo : public MCInstrInfo {
923918
}
924919

925920
protected:
926-
/// Target-dependent implementation for IsCopyInstr.
921+
/// Target-dependent implemenation for IsCopyInstr.
927922
/// If the specific machine instruction is a instruction that moves/copies
928-
/// value from one register to another register return destination and source
929-
/// registers as machine operands.
930-
virtual Optional<DestSourcePair>
931-
isCopyInstrImpl(const MachineInstr &MI) const {
932-
return None;
923+
/// value from one register to another register return true along with
924+
/// @Source machine operand and @Destination machine operand.
925+
virtual bool isCopyInstrImpl(const MachineInstr &MI,
926+
const MachineOperand *&Source,
927+
const MachineOperand *&Destination) const {
928+
return false;
933929
}
934930

935931
public:
936932
/// If the specific machine instruction is a instruction that moves/copies
937-
/// value from one register to another register return destination and source
938-
/// registers as machine operands.
939-
/// For COPY-instruction the method naturally returns destination and source
940-
/// registers as machine operands, for all other instructions the method calls
941-
/// target-dependent implementation.
942-
Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const {
933+
/// value from one register to another register return true along with
934+
/// @Source machine operand and @Destination machine operand.
935+
/// For COPY-instruction the method naturally returns true, for all other
936+
/// instructions the method calls target-dependent implementation.
937+
bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source,
938+
const MachineOperand *&Destination) const {
943939
if (MI.isCopy()) {
944-
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
940+
Destination = &MI.getOperand(0);
941+
Source = &MI.getOperand(1);
942+
return true;
945943
}
946-
return isCopyInstrImpl(MI);
944+
return isCopyInstrImpl(MI, Source, Destination);
947945
}
948946

949947
/// If the specific machine instruction is an instruction that adds an
950-
/// immediate value to its source operand and stores it in destination,
951-
/// return destination and source registers as machine operands along with
952-
/// \c Offset which has been added.
953-
virtual Optional<DestSourcePair> isAddImmediate(const MachineInstr &MI,
954-
int64_t &Offset) const {
955-
return None;
948+
/// immediate value to its \c Source operand and stores it in \c Destination,
949+
/// return true along with \c Destination and \c Source machine operand to
950+
/// which \c Offset has been added.
951+
virtual bool isAddImmediate(const MachineInstr &MI,
952+
const MachineOperand *&Destination,
953+
const MachineOperand *&Source,
954+
int64_t &Offset) const {
955+
return false;
956956
}
957957

958958
/// Store the specified register of the given register class to the specified

‎llvm/lib/CodeGen/LiveDebugValues.cpp

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -997,14 +997,10 @@ void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
997997
OpenRangesSet &OpenRanges,
998998
VarLocMap &VarLocIDs,
999999
TransferMap &Transfers) {
1000+
const MachineOperand *SrcRegOp, *DestRegOp;
10001001

1001-
auto DestSrc = TII->isCopyInstr(MI);
1002-
if (!DestSrc)
1003-
return;
1004-
1005-
const MachineOperand &DestRegOp = DestSrc->Destination;
1006-
const MachineOperand &SrcRegOp = DestSrc->Source;
1007-
if (!SrcRegOp.isKill() || !DestRegOp.isDef())
1002+
if (!TII->isCopyInstr(MI, SrcRegOp, DestRegOp) || !SrcRegOp->isKill() ||
1003+
!DestRegOp->isDef())
10081004
return;
10091005

10101006
auto isCalleeSavedReg = [&](unsigned Reg) {
@@ -1014,8 +1010,8 @@ void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
10141010
return false;
10151011
};
10161012

1017-
Register SrcReg = SrcRegOp.getReg();
1018-
Register DestReg = DestRegOp.getReg();
1013+
Register SrcReg = SrcRegOp->getReg();
1014+
Register DestReg = DestRegOp->getReg();
10191015

10201016
// We want to recognize instructions where destination register is callee
10211017
// saved register. If register that could be clobbered by the call is

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1124,13 +1124,14 @@ Optional<ParamLoadedValue>
11241124
TargetInstrInfo::describeLoadedValue(const MachineInstr &MI) const {
11251125
const MachineFunction *MF = MI.getMF();
11261126
DIExpression *Expr = DIExpression::get(MF->getFunction().getContext(), {});
1127+
const MachineOperand *SrcRegOp, *DestRegOp;
11271128
int64_t Offset;
11281129

1129-
if (auto DestSrc = isCopyInstr(MI)) {
1130-
return ParamLoadedValue(DestSrc->Source, Expr);
1131-
} else if (auto DestSrc = isAddImmediate(MI, Offset)) {
1130+
if (isCopyInstr(MI, SrcRegOp, DestRegOp)) {
1131+
return ParamLoadedValue(*SrcRegOp, Expr);
1132+
} else if (isAddImmediate(MI, DestRegOp, SrcRegOp, Offset)) {
11321133
Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
1133-
return ParamLoadedValue(DestSrc->Source, Expr);
1134+
return ParamLoadedValue(*SrcRegOp, Expr);
11341135
}
11351136

11361137
return None;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5952,33 +5952,39 @@ bool AArch64InstrInfo::shouldOutlineFromFunctionByDefault(
59525952
return MF.getFunction().hasMinSize();
59535953
}
59545954

5955-
Optional<DestSourcePair>
5956-
AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
5955+
bool AArch64InstrInfo::isCopyInstrImpl(
5956+
const MachineInstr &MI, const MachineOperand *&Source,
5957+
const MachineOperand *&Destination) const {
59575958

59585959
// AArch64::ORRWrs and AArch64::ORRXrs with WZR/XZR reg
59595960
// and zero immediate operands used as an alias for mov instruction.
59605961
if (MI.getOpcode() == AArch64::ORRWrs &&
59615962
MI.getOperand(1).getReg() == AArch64::WZR &&
59625963
MI.getOperand(3).getImm() == 0x0) {
5963-
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
5964+
Destination = &MI.getOperand(0);
5965+
Source = &MI.getOperand(2);
5966+
return true;
59645967
}
59655968

59665969
if (MI.getOpcode() == AArch64::ORRXrs &&
59675970
MI.getOperand(1).getReg() == AArch64::XZR &&
59685971
MI.getOperand(3).getImm() == 0x0) {
5969-
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
5972+
Destination = &MI.getOperand(0);
5973+
Source = &MI.getOperand(2);
5974+
return true;
59705975
}
59715976

5972-
return None;
5977+
return false;
59735978
}
59745979

5975-
Optional<DestSourcePair>
5976-
AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
5977-
int64_t &Offset) const {
5980+
bool AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
5981+
const MachineOperand *&Destination,
5982+
const MachineOperand *&Source,
5983+
int64_t &Offset) const {
59785984
int Sign = 1;
59795985
switch (MI.getOpcode()) {
59805986
default:
5981-
return None;
5987+
return false;
59825988
case AArch64::SUBWri:
59835989
case AArch64::SUBXri:
59845990
case AArch64::SUBSWri:
@@ -5992,14 +5998,16 @@ AArch64InstrInfo::isAddImmediate(const MachineInstr &MI,
59925998
// TODO: Third operand can be global address (usually some string).
59935999
if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
59946000
!MI.getOperand(2).isImm())
5995-
return None;
6001+
return false;
6002+
Source = &MI.getOperand(1);
59966003
Offset = MI.getOperand(2).getImm() * Sign;
59976004
int Shift = MI.getOperand(3).getImm();
59986005
assert((Shift == 0 || Shift == 12) && "Shift can be either 0 or 12");
59996006
Offset = Offset << Shift;
60006007
}
60016008
}
6002-
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
6009+
Destination = &MI.getOperand(0);
6010+
return true;
60036011
}
60046012

60056013
Optional<ParamLoadedValue>

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -265,8 +265,10 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
265265
/// on Windows.
266266
static bool isSEHInstruction(const MachineInstr &MI);
267267

268-
Optional<DestSourcePair> isAddImmediate(const MachineInstr &MI,
269-
int64_t &Offset) const override;
268+
bool isAddImmediate(const MachineInstr &MI,
269+
const MachineOperand *&Destination,
270+
const MachineOperand *&Source,
271+
int64_t &Offset) const override;
270272

271273
Optional<ParamLoadedValue>
272274
describeLoadedValue(const MachineInstr &MI) const override;
@@ -275,11 +277,11 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
275277
#include "AArch64GenInstrInfo.inc"
276278

277279
protected:
278-
/// If the specific machine instruction is an instruction that moves/copies
279-
/// value from one register to another register return destination and source
280-
/// registers as machine operands.
281-
Optional<DestSourcePair>
282-
isCopyInstrImpl(const MachineInstr &MI) const override;
280+
/// If the specific machine instruction is a instruction that moves/copies
281+
/// value from one register to another register return true along with
282+
/// @Source machine operand and @Destination machine operand.
283+
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
284+
const MachineOperand *&Destination) const override;
283285

284286
private:
285287
/// Sets the offsets on outlined instructions in \p MBB which use SP

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -993,8 +993,9 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
993993
Mov->addRegisterKilled(SrcReg, TRI);
994994
}
995995

996-
Optional<DestSourcePair>
997-
ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
996+
bool ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
997+
const MachineOperand *&Src,
998+
const MachineOperand *&Dest) const {
998999
// VMOVRRD is also a copy instruction but it requires
9991000
// special way of handling. It is more complex copy version
10001001
// and since that we are not considering it. For recognition
@@ -1005,8 +1006,10 @@ ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
10051006
if (!MI.isMoveReg() ||
10061007
(MI.getOpcode() == ARM::VORRq &&
10071008
MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1008-
return None;
1009-
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1009+
return false;
1010+
Dest = &MI.getOperand(0);
1011+
Src = &MI.getOperand(1);
1012+
return true;
10101013
}
10111014

10121015
const MachineInstrBuilder &
@@ -5347,27 +5350,30 @@ ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
53475350
return makeArrayRef(TargetFlags);
53485351
}
53495352

5350-
Optional<DestSourcePair>
5351-
ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
5352-
int64_t &Offset) const {
5353+
bool ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI,
5354+
const MachineOperand *&Destination,
5355+
const MachineOperand *&Source,
5356+
int64_t &Offset) const {
53535357
int Sign = 1;
53545358
unsigned Opcode = MI.getOpcode();
53555359

53565360
// We describe SUBri or ADDri instructions.
53575361
if (Opcode == ARM::SUBri)
53585362
Sign = -1;
53595363
else if (Opcode != ARM::ADDri)
5360-
return None;
5364+
return false;
53615365

53625366
// TODO: Third operand can be global address (usually some string). Since
53635367
// strings can be relocated we cannot calculate their offsets for
53645368
// now.
53655369
if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg() ||
53665370
!MI.getOperand(2).isImm())
5367-
return None;
5371+
return false;
53685372

5373+
Destination = &MI.getOperand(0);
5374+
Source = &MI.getOperand(1);
53695375
Offset = MI.getOperand(2).getImm() * Sign;
5370-
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
5376+
return true;
53715377
}
53725378

53735379
bool llvm::registerDefinedBetween(unsigned Reg,

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -99,11 +99,12 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
9999
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
100100
unsigned OpIdx1,
101101
unsigned OpIdx2) const override;
102-
/// If the specific machine instruction is an instruction that moves/copies
103-
/// value from one register to another register return destination and source
104-
/// registers as machine operands.
105-
Optional<DestSourcePair>
106-
isCopyInstrImpl(const MachineInstr &MI) const override;
102+
103+
/// If the specific machine instruction is a instruction that moves/copies
104+
/// value from one register to another register return true along with
105+
/// @Source machine operand and @Destination machine operand.
106+
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
107+
const MachineOperand *&Destination) const override;
107108

108109
public:
109110
// Return whether the target has an explicit NOP encoding.
@@ -455,8 +456,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
455456
return MI.getOperand(3).getReg();
456457
}
457458

458-
Optional<DestSourcePair> isAddImmediate(const MachineInstr &MI,
459-
int64_t &Offset) const override;
459+
bool isAddImmediate(const MachineInstr &MI,
460+
const MachineOperand *&Destination,
461+
const MachineOperand *&Source,
462+
int64_t &Offset) const override;
460463
};
461464

462465
/// Get the operands corresponding to the given \p Pred value. By default, the

‎llvm/lib/Target/Mips/Mips16InstrInfo.cpp

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -96,11 +96,15 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
9696
MIB.addReg(SrcReg, getKillRegState(KillSrc));
9797
}
9898

99-
Optional<DestSourcePair>
100-
Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
101-
if (MI.isMoveReg())
102-
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
103-
return None;
99+
bool Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
100+
const MachineOperand *&Src,
101+
const MachineOperand *&Dest) const {
102+
if (MI.isMoveReg()) {
103+
Dest = &MI.getOperand(0);
104+
Src = &MI.getOperand(1);
105+
return true;
106+
}
107+
return false;
104108
}
105109

106110
void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,

‎llvm/lib/Target/Mips/Mips16InstrInfo.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -104,9 +104,10 @@ class Mips16InstrInfo : public MipsInstrInfo {
104104

105105
protected:
106106
/// If the specific machine instruction is a instruction that moves/copies
107-
/// value from one register to another register return destination and source
108-
/// registers as machine operands.
109-
Optional<DestSourcePair> isCopyInstrImpl(const MachineInstr &MI) const override;
107+
/// value from one register to another register return true along with
108+
/// @Source machine operand and @Destination machine operand.
109+
bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
110+
const MachineOperand *&Destination) const override;
110111

111112
private:
112113
unsigned getAnalyzableBrOpc(unsigned Opc) const override;

‎llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -221,24 +221,29 @@ static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
221221
/// We check for the common case of 'or', as it's MIPS' preferred instruction
222222
/// for GPRs but we have to check the operands to ensure that is the case.
223223
/// Other move instructions for MIPS are directly identifiable.
224-
Optional<DestSourcePair>
225-
MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
224+
bool MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
225+
const MachineOperand *&Src,
226+
const MachineOperand *&Dest) const {
226227
bool isDSPControlWrite = false;
227228
// Condition is made to match the creation of WRDSP/RDDSP copy instruction
228229
// from copyPhysReg function.
229230
if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
230-
if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4))
231-
return None;
231+
if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
232+
return false;
232233
else if (isDSPControlWrite) {
233-
return DestSourcePair{MI.getOperand(2), MI.getOperand(0)};
234-
234+
Src = &MI.getOperand(0);
235+
Dest = &MI.getOperand(2);
235236
} else {
236-
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
237+
Dest = &MI.getOperand(0);
238+
Src = &MI.getOperand(2);
237239
}
240+
return true;
238241
} else if (MI.isMoveReg() || isORCopyInst(MI)) {
239-
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
242+
Dest = &MI.getOperand(0);
243+
Src = &MI.getOperand(1);
244+
return true;
240245
}
241-
return None;
246+
return false;
242247
}
243248

244249
void MipsSEInstrInfo::

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