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[Sparc] Fix "Cannot select" error for AtomicFence on 32-bit V9
Summary: This also adds testing of 32-bit V9 atomic lowering, splitting the 64-bit-only tests out into their own file. Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: hiraditya, fedor.sergeev, jfb, llvm-commits, glaubitz Tags: #llvm Differential Revision: https://reviews.llvm.org/D69352
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4 files changed

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‎llvm/lib/Target/Sparc/SparcInstr64Bit.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -497,8 +497,6 @@ let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
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let Predicates = [Is64Bit] in {
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500-
def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
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// atomic_load_64 addr -> load addr
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def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
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def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;

‎llvm/lib/Target/Sparc/SparcInstrInfo.td

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@@ -1678,6 +1678,9 @@ def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
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let Predicates = [HasNoV9] in
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def : Pat<(atomic_fence imm, imm), (STBAR)>;
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let Predicates = [HasV9] in
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def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
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// atomic_load addr -> load addr
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def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
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def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;

‎llvm/test/CodeGen/SPARC/64atomics.ll

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
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; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: test_atomic_i64
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; CHECK: ldx [%o0]
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; CHECK: membar
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; CHECK: ldx [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: stx {{.+}}, [%o2]
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define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
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entry:
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%0 = load atomic i64, i64* %ptr1 acquire, align 8
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%1 = load atomic i64, i64* %ptr2 acquire, align 8
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%2 = add i64 %0, %1
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store atomic i64 %2, i64* %ptr3 release, align 8
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ret i64 %2
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}
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; CHECK-LABEL: test_cmpxchg_i64
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; CHECK: mov 123, [[R:%[gilo][0-7]]]
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; CHECK: casx [%o1], %o0, [[R]]
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define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
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entry:
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%pair = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
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%b = extractvalue { i64, i1 } %pair, 0
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ret i64 %b
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}
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; CHECK-LABEL: test_swap_i64
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; CHECK: casx [%o1],
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define i64 @test_swap_i64(i64 %a, i64* %ptr) {
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entry:
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%b = atomicrmw xchg i64* %ptr, i64 42 monotonic
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ret i64 %b
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}
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; CHECK-LABEL: test_load_sub_64
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; CHECK: membar
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; CHECK: sub
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; CHECK: casx [%o0]
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; CHECK: membar
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define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw sub i64* %p, i64 %v seq_cst
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ret i64 %0
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}
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; CHECK-LABEL: test_load_max_64
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; CHECK: membar
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; CHECK: cmp
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; CHECK: movg %xcc
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; CHECK: casx [%o0]
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; CHECK: membar
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define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw max i64* %p, i64 %v seq_cst
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ret i64 %0
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}

‎llvm/test/CodeGen/SPARC/atomics.ll

Lines changed: 1 addition & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
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; RUN: llc < %s -march=sparc -mcpu=v9 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: test_atomic_i8
@@ -48,22 +49,6 @@ entry:
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ret i32 %2
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}
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; CHECK-LABEL: test_atomic_i64
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; CHECK: ldx [%o0]
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; CHECK: membar
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; CHECK: ldx [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: stx {{.+}}, [%o2]
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define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
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entry:
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%0 = load atomic i64, i64* %ptr1 acquire, align 8
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%1 = load atomic i64, i64* %ptr2 acquire, align 8
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%2 = add i64 %0, %1
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store atomic i64 %2, i64* %ptr3 release, align 8
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ret i64 %2
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}
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;; TODO: the "move %icc" and related instructions are totally
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;; redundant here. There's something weird happening in optimization
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;; of the success value of cmpxchg.
@@ -159,17 +144,6 @@ entry:
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ret i32 %b
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}
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; CHECK-LABEL: test_cmpxchg_i64
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; CHECK: mov 123, [[R:%[gilo][0-7]]]
164-
; CHECK: casx [%o1], %o0, [[R]]
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define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
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entry:
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%pair = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
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%b = extractvalue { i64, i1 } %pair, 0
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ret i64 %b
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}
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173147
; CHECK-LABEL: test_swap_i8
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; CHECK: mov 42, [[R:%[gilo][0-7]]]
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; CHECK: cas
@@ -200,15 +174,6 @@ entry:
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ret i32 %b
201175
}
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; CHECK-LABEL: test_swap_i64
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; CHECK: casx [%o1],
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define i64 @test_swap_i64(i64 %a, i64* %ptr) {
207-
entry:
208-
%b = atomicrmw xchg i64* %ptr, i64 42 monotonic
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ret i64 %b
210-
}
211-
212177
; CHECK-LABEL: test_load_sub_i8
213178
; CHECK: membar
214179
; CHECK: .L{{.*}}:
@@ -246,17 +211,6 @@ entry:
246211
ret i32 %0
247212
}
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; CHECK-LABEL: test_load_sub_64
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; CHECK: membar
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; CHECK: sub
252-
; CHECK: casx [%o0]
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; CHECK: membar
254-
define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
255-
entry:
256-
%0 = atomicrmw sub i64* %p, i64 %v seq_cst
257-
ret i64 %0
258-
}
259-
260214
; CHECK-LABEL: test_load_xor_32
261215
; CHECK: membar
262216
; CHECK: xor
@@ -292,18 +246,6 @@ entry:
292246
ret i32 %0
293247
}
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295-
; CHECK-LABEL: test_load_max_64
296-
; CHECK: membar
297-
; CHECK: cmp
298-
; CHECK: movg %xcc
299-
; CHECK: casx [%o0]
300-
; CHECK: membar
301-
define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
302-
entry:
303-
%0 = atomicrmw max i64* %p, i64 %v seq_cst
304-
ret i64 %0
305-
}
306-
307249
; CHECK-LABEL: test_load_umin_32
308250
; CHECK: membar
309251
; CHECK: cmp

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