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Merge commit '9f3482343cba' from apple/master into swift/master-next
2 parents 92c6007 + 9f34823 commit 84f7df2

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‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -5877,34 +5877,35 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
58775877
case Intrinsic::amdgcn_fdiv_fast:
58785878
return lowerFDIV_FAST(Op, DAG);
58795879
case Intrinsic::amdgcn_interp_mov: {
5880-
SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
5881-
SDValue Glue = M0.getValue(1);
5880+
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5881+
Op.getOperand(4), SDValue());
58825882
return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32, Op.getOperand(1),
5883-
Op.getOperand(2), Op.getOperand(3), Glue);
5883+
Op.getOperand(2), Op.getOperand(3), ToM0.getValue(1));
58845884
}
58855885
case Intrinsic::amdgcn_interp_p1: {
5886-
SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
5887-
SDValue Glue = M0.getValue(1);
5886+
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5887+
Op.getOperand(4), SDValue());
58885888
return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
5889-
Op.getOperand(2), Op.getOperand(3), Glue);
5889+
Op.getOperand(2), Op.getOperand(3), ToM0.getValue(1));
58905890
}
58915891
case Intrinsic::amdgcn_interp_p2: {
5892-
SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
5893-
SDValue Glue = SDValue(M0.getNode(), 1);
5892+
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5893+
Op.getOperand(5), SDValue());
58945894
return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
58955895
Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
5896-
Glue);
5896+
ToM0.getValue(1));
58975897
}
58985898
case Intrinsic::amdgcn_interp_p1_f16: {
5899-
SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
5900-
SDValue Glue = M0.getValue(1);
5899+
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5900+
Op.getOperand(5), SDValue());
5901+
59015902
if (getSubtarget()->getLDSBankCount() == 16) {
59025903
// 16 bank LDS
59035904
SDValue S = DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
59045905
DAG.getConstant(2, DL, MVT::i32), // P0
59055906
Op.getOperand(2), // Attrchan
59065907
Op.getOperand(3), // Attr
5907-
Glue);
5908+
ToM0.getValue(1));
59085909
SDValue Ops[] = {
59095910
Op.getOperand(1), // Src0
59105911
Op.getOperand(2), // Attrchan
@@ -5927,14 +5928,14 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
59275928
Op.getOperand(4), // high
59285929
DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
59295930
DAG.getTargetConstant(0, DL, MVT::i32), // $omod
5930-
Glue
5931+
ToM0.getValue(1)
59315932
};
59325933
return DAG.getNode(AMDGPUISD::INTERP_P1LL_F16, DL, MVT::f32, Ops);
59335934
}
59345935
}
59355936
case Intrinsic::amdgcn_interp_p2_f16: {
5936-
SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(6));
5937-
SDValue Glue = SDValue(M0.getNode(), 1);
5937+
SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5938+
Op.getOperand(6), SDValue());
59385939
SDValue Ops[] = {
59395940
Op.getOperand(2), // Src0
59405941
Op.getOperand(3), // Attrchan
@@ -5944,7 +5945,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
59445945
DAG.getTargetConstant(0, DL, MVT::i32), // $src2_modifiers
59455946
Op.getOperand(5), // high
59465947
DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
5947-
Glue
5948+
ToM0.getValue(1)
59485949
};
59495950
return DAG.getNode(AMDGPUISD::INTERP_P2_F16, DL, MVT::f16, Ops);
59505951
}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@
66
define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
77
; GFX9-32BANK-LABEL: interp_f16:
88
; GFX9-32BANK: ; %bb.0: ; %main_body
9-
; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
109
; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
10+
; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
1111
; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
1212
; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y
1313
; GFX9-32BANK-NEXT: v_mov_b32_e32 v2, s1
@@ -20,8 +20,8 @@ define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0)
2020
;
2121
; GFX8-32BANK-LABEL: interp_f16:
2222
; GFX8-32BANK: ; %bb.0: ; %main_body
23-
; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
2423
; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
24+
; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
2525
; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
2626
; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y
2727
; GFX8-32BANK-NEXT: v_mov_b32_e32 v2, s1
@@ -119,8 +119,8 @@ main_body:
119119
define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
120120
; GFX9-32BANK-LABEL: interp_p2_m0_setup:
121121
; GFX9-32BANK: ; %bb.0: ; %main_body
122-
; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
123122
; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
123+
; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
124124
; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
125125
; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
126126
; GFX9-32BANK-NEXT: ;;#ASMSTART
@@ -136,8 +136,8 @@ define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 in
136136
;
137137
; GFX8-32BANK-LABEL: interp_p2_m0_setup:
138138
; GFX8-32BANK: ; %bb.0: ; %main_body
139-
; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
140139
; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
140+
; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
141141
; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
142142
; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
143143
; GFX8-32BANK-NEXT: ;;#ASMSTART

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