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[AArch64][SVE2] Implement remaining SVE2 floating-point intrinsics
Summary: Adds the following intrinsics: - faddp - fmaxp, fminp, fmaxnmp & fminnmp - fmlalb, fmlalt, fmlslb & fmlslt - flogb Reviewers: huntergr, sdesmalen, dancgr, efriedma Reviewed By: sdesmalen Subscribers: efriedma, tschuett, kristof.beyls, hiraditya, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70253
1 parent cc3c935 commit 8881ac9

6 files changed

+447
-17
lines changed

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -951,6 +951,25 @@ class AdvSIMD_GatherLoad_64bitOffset_Intrinsic
951951
],
952952
[IntrReadMem, IntrArgMemOnly]>;
953953

954+
class SVE2_3VectorArg_Long_Intrinsic
955+
: Intrinsic<[llvm_anyvector_ty],
956+
[LLVMMatchType<0>,
957+
LLVMSubdivide2VectorType<0>,
958+
LLVMSubdivide2VectorType<0>],
959+
[IntrNoMem]>;
960+
961+
class SVE2_3VectorArgIndexed_Long_Intrinsic
962+
: Intrinsic<[llvm_anyvector_ty],
963+
[LLVMMatchType<0>,
964+
LLVMSubdivide2VectorType<0>,
965+
LLVMSubdivide2VectorType<0>,
966+
llvm_i32_ty],
967+
[IntrNoMem]>;
968+
969+
// NOTE: There is no relationship between these intrinsics beyond an attempt
970+
// to reuse currently identical class definitions.
971+
class AdvSIMD_SVE_LOGB_Intrinsic : AdvSIMD_SVE_CNT_Intrinsic;
972+
954973
// This class of intrinsics are not intended to be useful within LLVM IR but
955974
// are instead here to support some of the more regid parts of the ACLE.
956975
class Builtin_SVCVT<string name, LLVMType OUT, LLVMType IN>
@@ -1191,4 +1210,33 @@ def int_aarch64_sve_ld1_gather : AdvSIMD_GatherLoad_64bitOffset_Intrinsic;
11911210

11921211
// scalar + vector, 64 bit scaled offsets
11931212
def int_aarch64_sve_ld1_gather_index : AdvSIMD_GatherLoad_64bitOffset_Intrinsic;
1213+
1214+
//
1215+
// SVE2 - Non-widening pairwise arithmetic
1216+
//
1217+
1218+
def int_aarch64_sve_faddp : AdvSIMD_Pred2VectorArg_Intrinsic;
1219+
def int_aarch64_sve_fmaxp : AdvSIMD_Pred2VectorArg_Intrinsic;
1220+
def int_aarch64_sve_fmaxnmp : AdvSIMD_Pred2VectorArg_Intrinsic;
1221+
def int_aarch64_sve_fminp : AdvSIMD_Pred2VectorArg_Intrinsic;
1222+
def int_aarch64_sve_fminnmp : AdvSIMD_Pred2VectorArg_Intrinsic;
1223+
1224+
//
1225+
// SVE2 - Floating-point widening multiply-accumulate
1226+
//
1227+
1228+
def int_aarch64_sve_fmlalb : SVE2_3VectorArg_Long_Intrinsic;
1229+
def int_aarch64_sve_fmlalb_lane : SVE2_3VectorArgIndexed_Long_Intrinsic;
1230+
def int_aarch64_sve_fmlalt : SVE2_3VectorArg_Long_Intrinsic;
1231+
def int_aarch64_sve_fmlalt_lane : SVE2_3VectorArgIndexed_Long_Intrinsic;
1232+
def int_aarch64_sve_fmlslb : SVE2_3VectorArg_Long_Intrinsic;
1233+
def int_aarch64_sve_fmlslb_lane : SVE2_3VectorArgIndexed_Long_Intrinsic;
1234+
def int_aarch64_sve_fmlslt : SVE2_3VectorArg_Long_Intrinsic;
1235+
def int_aarch64_sve_fmlslt_lane : SVE2_3VectorArgIndexed_Long_Intrinsic;
1236+
1237+
//
1238+
// SVE2 - Floating-point integer binary logarithm
1239+
//
1240+
1241+
def int_aarch64_sve_flogb : AdvSIMD_SVE_LOGB_Intrinsic;
11941242
}

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1427,7 +1427,7 @@ let Predicates = [HasSVE2] in {
14271427
defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">;
14281428

14291429
// SVE2 floating-point base 2 logarithm as integer
1430-
defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
1430+
defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb", int_aarch64_sve_flogb>;
14311431

14321432
// SVE2 floating-point convert precision
14331433
defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding_top<"fcvtxnt", "int_aarch64_sve_fcvtxnt">;
@@ -1436,23 +1436,23 @@ let Predicates = [HasSVE2] in {
14361436
defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt", "int_aarch64_sve_fcvtlt">;
14371437

14381438
// SVE2 floating-point pairwise operations
1439-
defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">;
1440-
defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp">;
1441-
defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp">;
1442-
defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">;
1443-
defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">;
1439+
defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp", int_aarch64_sve_faddp>;
1440+
defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp", int_aarch64_sve_fmaxnmp>;
1441+
defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp", int_aarch64_sve_fminnmp>;
1442+
defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp", int_aarch64_sve_fmaxp>;
1443+
defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp", int_aarch64_sve_fminp>;
14441444

14451445
// SVE2 floating-point multiply-add long (indexed)
1446-
def FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb">;
1447-
def FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt">;
1448-
def FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb">;
1449-
def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">;
1446+
defm FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb", int_aarch64_sve_fmlalb_lane>;
1447+
defm FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt", int_aarch64_sve_fmlalt_lane>;
1448+
defm FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb", int_aarch64_sve_fmlslb_lane>;
1449+
defm FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt", int_aarch64_sve_fmlslt_lane>;
14501450

14511451
// SVE2 floating-point multiply-add long
1452-
def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">;
1453-
def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">;
1454-
def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">;
1455-
def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">;
1452+
defm FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb", int_aarch64_sve_fmlalb>;
1453+
defm FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt", int_aarch64_sve_fmlalt>;
1454+
defm FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb", int_aarch64_sve_fmlslb>;
1455+
defm FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt", int_aarch64_sve_fmlslt>;
14561456

14571457
// SVE2 bitwise ternary operations
14581458
defm EOR3_ZZZZ_D : sve2_int_bitwise_ternary_op<0b000, "eor3">;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 28 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -310,6 +310,12 @@ class SVE_3_Op_Imm_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
310310
: Pat<(vtd (op vt1:$Op1, vt2:$Op2, (vt3 ImmTy:$Op3))),
311311
(inst $Op1, $Op2, ImmTy:$Op3)>;
312312

313+
class SVE_4_Op_Imm_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
314+
ValueType vt2, ValueType vt3, ValueType vt4,
315+
Operand ImmTy, Instruction inst>
316+
: Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
317+
(inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
318+
313319
def SVEDup0Undef : ComplexPattern<i64, 0, "SelectDupZeroOrUndef", []>;
314320

315321
//===----------------------------------------------------------------------===//
@@ -1695,10 +1701,14 @@ class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm,
16951701
let ElementSize = zprty.ElementSize;
16961702
}
16971703

1698-
multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> {
1704+
multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm, SDPatternOperator op> {
16991705
def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>;
17001706
def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>;
17011707
def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>;
1708+
1709+
def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H)>;
1710+
def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
1711+
def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
17021712
}
17031713

17041714
//===----------------------------------------------------------------------===//
@@ -1707,7 +1717,7 @@ multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> {
17071717

17081718
class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
17091719
: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
1710-
VectorIndexH:$iop),
1720+
VectorIndexH32b:$iop),
17111721
asm, "\t$Zda, $Zn, $Zm$iop",
17121722
"",
17131723
[]>, Sched<[]> {
@@ -1731,6 +1741,12 @@ class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
17311741
let ElementSize = ElementSizeNone;
17321742
}
17331743

1744+
multiclass sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm,
1745+
SDPatternOperator op> {
1746+
def NAME : sve2_fp_mla_long_by_indexed_elem<opc, asm>;
1747+
def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, nxv8f16, nxv8f16, i32, VectorIndexH32b, !cast<Instruction>(NAME)>;
1748+
}
1749+
17341750
//===----------------------------------------------------------------------===//
17351751
// SVE2 Floating Point Widening Multiply-Add Group
17361752
//===----------------------------------------------------------------------===//
@@ -1757,6 +1773,11 @@ class sve2_fp_mla_long<bits<2> opc, string asm>
17571773
let ElementSize = ElementSizeNone;
17581774
}
17591775

1776+
multiclass sve2_fp_mla_long<bits<2> opc, string asm, SDPatternOperator op> {
1777+
def NAME : sve2_fp_mla_long<opc, asm>;
1778+
def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv8f16, nxv8f16, !cast<Instruction>(NAME)>;
1779+
}
1780+
17601781
//===----------------------------------------------------------------------===//
17611782
// SVE Stack Allocation Group
17621783
//===----------------------------------------------------------------------===//
@@ -1871,10 +1892,14 @@ multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm, SDPatternOperator op> {
18711892
def : SVE_3_Op_Pat<nxv2f64, op, nxv2f64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
18721893
}
18731894

1874-
multiclass sve2_fp_flogb<string asm> {
1895+
multiclass sve2_fp_flogb<string asm, SDPatternOperator op> {
18751896
def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>;
18761897
def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>;
18771898
def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>;
1899+
1900+
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
1901+
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
1902+
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
18781903
}
18791904

18801905
multiclass sve2_fp_convert_down_odd_rounding<string asm, string op> {

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
;RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 < %s | FileCheck %s
2+
3+
;
4+
; FLOGB
5+
;
6+
7+
define <vscale x 8 x i16> @flogb_f16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b) {
8+
; CHECK-LABEL: flogb_f16:
9+
; CHECK: flogb z0.h, p0/m, z1.h
10+
; CHECK-NEXT: ret
11+
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> %a,
12+
<vscale x 8 x i1> %pg,
13+
<vscale x 8 x half> %b)
14+
ret <vscale x 8 x i16> %out
15+
}
16+
17+
define <vscale x 4 x i32> @flogb_f32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
18+
; CHECK-LABEL: flogb_f32:
19+
; CHECK: flogb z0.s, p0/m, z1.s
20+
; CHECK-NEXT: ret
21+
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> %a,
22+
<vscale x 4 x i1> %pg,
23+
<vscale x 4 x float> %b)
24+
ret <vscale x 4 x i32> %out
25+
}
26+
27+
define <vscale x 2 x i64> @flogb_f64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
28+
; CHECK-LABEL: flogb_f64:
29+
; CHECK: flogb z0.d, p0/m, z1.d
30+
; CHECK-NEXT: ret
31+
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> %a,
32+
<vscale x 2 x i1> %pg,
33+
<vscale x 2 x double> %b)
34+
ret <vscale x 2 x i64> %out
35+
}
36+
37+
declare <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>)
38+
declare <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>)
39+
declare <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x double>)

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll

Lines changed: 127 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,127 @@
1+
;RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
2+
3+
;
4+
; FMLALB (Vectors)
5+
;
6+
7+
define <vscale x 4 x float> @fmlalb_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
8+
; CHECK-LABEL: fmlalb_h:
9+
; CHECK: fmlalb z0.s, z1.h, z2.h
10+
; CHECK-NEXT: ret
11+
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.nxv4f32(<vscale x 4 x float> %a,
12+
<vscale x 8 x half> %b,
13+
<vscale x 8 x half> %c)
14+
ret <vscale x 4 x float> %out
15+
}
16+
17+
;
18+
; FMLALB (Indexed)
19+
;
20+
21+
define <vscale x 4 x float> @fmlalb_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
22+
; CHECK-LABEL: fmlalb_lane_h:
23+
; CHECK: fmlalb z0.s, z1.h, z2.h[0]
24+
; CHECK-NEXT: ret
25+
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.lane.nxv4f32(<vscale x 4 x float> %a,
26+
<vscale x 8 x half> %b,
27+
<vscale x 8 x half> %c,
28+
i32 0)
29+
ret <vscale x 4 x float> %out
30+
}
31+
32+
;
33+
; FMLALT (Vectors)
34+
;
35+
36+
define <vscale x 4 x float> @fmlalt_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
37+
; CHECK-LABEL: fmlalt_h:
38+
; CHECK: fmlalt z0.s, z1.h, z2.h
39+
; CHECK-NEXT: ret
40+
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.nxv4f32(<vscale x 4 x float> %a,
41+
<vscale x 8 x half> %b,
42+
<vscale x 8 x half> %c)
43+
ret <vscale x 4 x float> %out
44+
}
45+
46+
;
47+
; FMLALT (Indexed)
48+
;
49+
50+
define <vscale x 4 x float> @fmlalt_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
51+
; CHECK-LABEL: fmlalt_lane_h:
52+
; CHECK: fmlalt z0.s, z1.h, z2.h[1]
53+
; CHECK-NEXT: ret
54+
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.lane.nxv4f32(<vscale x 4 x float> %a,
55+
<vscale x 8 x half> %b,
56+
<vscale x 8 x half> %c,
57+
i32 1)
58+
ret <vscale x 4 x float> %out
59+
}
60+
61+
;
62+
; FMLSLB (Vectors)
63+
;
64+
65+
define <vscale x 4 x float> @fmlslb_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
66+
; CHECK-LABEL: fmlslb_h:
67+
; CHECK: fmlslb z0.s, z1.h, z2.h
68+
; CHECK-NEXT: ret
69+
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.nxv4f32(<vscale x 4 x float> %a,
70+
<vscale x 8 x half> %b,
71+
<vscale x 8 x half> %c)
72+
ret <vscale x 4 x float> %out
73+
}
74+
75+
;
76+
; FMLSLB (Indexed)
77+
;
78+
79+
define <vscale x 4 x float> @fmlslb_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
80+
; CHECK-LABEL: fmlslb_lane_h:
81+
; CHECK: fmlslb z0.s, z1.h, z2.h[2]
82+
; CHECK-NEXT: ret
83+
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.lane.nxv4f32(<vscale x 4 x float> %a,
84+
<vscale x 8 x half> %b,
85+
<vscale x 8 x half> %c,
86+
i32 2)
87+
ret <vscale x 4 x float> %out
88+
}
89+
90+
;
91+
; FMLSLT (Vectors)
92+
;
93+
94+
define <vscale x 4 x float> @fmlslt_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
95+
; CHECK-LABEL: fmlslt_h:
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; CHECK: fmlslt z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c)
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ret <vscale x 4 x float> %out
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}
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;
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; FMLSLT (Indexed)
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;
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define <vscale x 4 x float> @fmlslt_lane_h(<vscale x 4 x float> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) {
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; CHECK-LABEL: fmlslt_lane_h:
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; CHECK: fmlslt z0.s, z1.h, z2.h[3]
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.lane.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 8 x half> %b,
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<vscale x 8 x half> %c,
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i32 3)
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ret <vscale x 4 x float> %out
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalb.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlalt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslb.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.fmlslt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 8 x half>, <vscale x 8 x half>, i32)

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