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[WebAssembly] Narrowing and widening SIMD ops
Summary: Implements target-specific LLVM intrinsics and clang builtins for these new SIMD operations, as described at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D67425 llvm-svn: 371906
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‎clang/include/clang/Basic/BuiltinsWebAssembly.def

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,5 +118,19 @@ TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i32x4_f32x4, "V4iV4f", "nc", "sim
118118
TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i64x2_f64x2, "V2LLiV2d", "nc", "unimplemented-simd128")
119119
TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i64x2_f64x2, "V2LLiV2d", "nc", "unimplemented-simd128")
120120

121+
TARGET_BUILTIN(__builtin_wasm_narrow_s_i8x16_i16x8, "V16cV8sV8s", "nc", "simd128")
122+
TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16cV8sV8s", "nc", "simd128")
123+
TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
124+
TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
125+
126+
TARGET_BUILTIN(__builtin_wasm_widen_low_s_i16x8_i8x16, "V8sV16c", "nc", "simd128")
127+
TARGET_BUILTIN(__builtin_wasm_widen_high_s_i16x8_i8x16, "V8sV16c", "nc", "simd128")
128+
TARGET_BUILTIN(__builtin_wasm_widen_low_u_i16x8_i8x16, "V8sV16c", "nc", "simd128")
129+
TARGET_BUILTIN(__builtin_wasm_widen_high_u_i16x8_i8x16, "V8sV16c", "nc", "simd128")
130+
TARGET_BUILTIN(__builtin_wasm_widen_low_s_i32x4_i16x8, "V4iV8s", "nc", "simd128")
131+
TARGET_BUILTIN(__builtin_wasm_widen_high_s_i32x4_i16x8, "V4iV8s", "nc", "simd128")
132+
TARGET_BUILTIN(__builtin_wasm_widen_low_u_i32x4_i16x8, "V4iV8s", "nc", "simd128")
133+
TARGET_BUILTIN(__builtin_wasm_widen_high_u_i32x4_i16x8, "V4iV8s", "nc", "simd128")
134+
121135
#undef BUILTIN
122136
#undef TARGET_BUILTIN

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14196,6 +14196,63 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
1419614196
Function *Callee = CGM.getIntrinsic(IntNo, A->getType());
1419714197
return Builder.CreateCall(Callee, {A, B, C});
1419814198
}
14199+
case WebAssembly::BI__builtin_wasm_narrow_s_i8x16_i16x8:
14200+
case WebAssembly::BI__builtin_wasm_narrow_u_i8x16_i16x8:
14201+
case WebAssembly::BI__builtin_wasm_narrow_s_i16x8_i32x4:
14202+
case WebAssembly::BI__builtin_wasm_narrow_u_i16x8_i32x4: {
14203+
Value *Low = EmitScalarExpr(E->getArg(0));
14204+
Value *High = EmitScalarExpr(E->getArg(1));
14205+
unsigned IntNo;
14206+
switch (BuiltinID) {
14207+
case WebAssembly::BI__builtin_wasm_narrow_s_i8x16_i16x8:
14208+
case WebAssembly::BI__builtin_wasm_narrow_s_i16x8_i32x4:
14209+
IntNo = Intrinsic::wasm_narrow_signed;
14210+
break;
14211+
case WebAssembly::BI__builtin_wasm_narrow_u_i8x16_i16x8:
14212+
case WebAssembly::BI__builtin_wasm_narrow_u_i16x8_i32x4:
14213+
IntNo = Intrinsic::wasm_narrow_unsigned;
14214+
break;
14215+
default:
14216+
llvm_unreachable("unexpected builtin ID");
14217+
}
14218+
Function *Callee =
14219+
CGM.getIntrinsic(IntNo, {ConvertType(E->getType()), Low->getType()});
14220+
return Builder.CreateCall(Callee, {Low, High});
14221+
}
14222+
case WebAssembly::BI__builtin_wasm_widen_low_s_i16x8_i8x16:
14223+
case WebAssembly::BI__builtin_wasm_widen_high_s_i16x8_i8x16:
14224+
case WebAssembly::BI__builtin_wasm_widen_low_u_i16x8_i8x16:
14225+
case WebAssembly::BI__builtin_wasm_widen_high_u_i16x8_i8x16:
14226+
case WebAssembly::BI__builtin_wasm_widen_low_s_i32x4_i16x8:
14227+
case WebAssembly::BI__builtin_wasm_widen_high_s_i32x4_i16x8:
14228+
case WebAssembly::BI__builtin_wasm_widen_low_u_i32x4_i16x8:
14229+
case WebAssembly::BI__builtin_wasm_widen_high_u_i32x4_i16x8: {
14230+
Value *Vec = EmitScalarExpr(E->getArg(0));
14231+
unsigned IntNo;
14232+
switch (BuiltinID) {
14233+
case WebAssembly::BI__builtin_wasm_widen_low_s_i16x8_i8x16:
14234+
case WebAssembly::BI__builtin_wasm_widen_low_s_i32x4_i16x8:
14235+
IntNo = Intrinsic::wasm_widen_low_signed;
14236+
break;
14237+
case WebAssembly::BI__builtin_wasm_widen_high_s_i16x8_i8x16:
14238+
case WebAssembly::BI__builtin_wasm_widen_high_s_i32x4_i16x8:
14239+
IntNo = Intrinsic::wasm_widen_high_signed;
14240+
break;
14241+
case WebAssembly::BI__builtin_wasm_widen_low_u_i16x8_i8x16:
14242+
case WebAssembly::BI__builtin_wasm_widen_low_u_i32x4_i16x8:
14243+
IntNo = Intrinsic::wasm_widen_low_unsigned;
14244+
break;
14245+
case WebAssembly::BI__builtin_wasm_widen_high_u_i16x8_i8x16:
14246+
case WebAssembly::BI__builtin_wasm_widen_high_u_i32x4_i16x8:
14247+
IntNo = Intrinsic::wasm_widen_high_unsigned;
14248+
break;
14249+
default:
14250+
llvm_unreachable("unexpected builtin ID");
14251+
}
14252+
Function *Callee =
14253+
CGM.getIntrinsic(IntNo, {ConvertType(E->getType()), Vec->getType()});
14254+
return Builder.CreateCall(Callee, Vec);
14255+
}
1419914256
default:
1420014257
return nullptr;
1420114258
}

‎clang/test/CodeGen/builtins-wasm.c

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -463,3 +463,79 @@ i64x2 trunc_saturate_u_i64x2_f64x2(f64x2 f) {
463463
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double> %f)
464464
// WEBASSEMBLY-NEXT: ret
465465
}
466+
467+
i8x16 narrow_s_i8x16_i16x8(i16x8 low, i16x8 high) {
468+
return __builtin_wasm_narrow_s_i8x16_i16x8(low, high);
469+
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
470+
// WEBASSEMBLY-SAME: <8 x i16> %low, <8 x i16> %high)
471+
// WEBASSEMBLY: ret
472+
}
473+
474+
i8x16 narrow_u_i8x16_i16x8(i16x8 low, i16x8 high) {
475+
return __builtin_wasm_narrow_u_i8x16_i16x8(low, high);
476+
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(
477+
// WEBASSEMBLY-SAME: <8 x i16> %low, <8 x i16> %high)
478+
// WEBASSEMBLY: ret
479+
}
480+
481+
i16x8 narrow_s_i16x8_i32x4(i32x4 low, i32x4 high) {
482+
return __builtin_wasm_narrow_s_i16x8_i32x4(low, high);
483+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(
484+
// WEBASSEMBLY-SAME: <4 x i32> %low, <4 x i32> %high)
485+
// WEBASSEMBLY: ret
486+
}
487+
488+
i16x8 narrow_u_i16x8_i32x4(i32x4 low, i32x4 high) {
489+
return __builtin_wasm_narrow_u_i16x8_i32x4(low, high);
490+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(
491+
// WEBASSEMBLY-SAME: <4 x i32> %low, <4 x i32> %high)
492+
// WEBASSEMBLY: ret
493+
}
494+
495+
i16x8 widen_low_s_i16x8_i8x16(i8x16 v) {
496+
return __builtin_wasm_widen_low_s_i16x8_i8x16(v);
497+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8> %v)
498+
// WEBASSEMBLY: ret
499+
}
500+
501+
i16x8 widen_high_s_i16x8_i8x16(i8x16 v) {
502+
return __builtin_wasm_widen_high_s_i16x8_i8x16(v);
503+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8> %v)
504+
// WEBASSEMBLY: ret
505+
}
506+
507+
i16x8 widen_low_u_i16x8_i8x16(i8x16 v) {
508+
return __builtin_wasm_widen_low_u_i16x8_i8x16(v);
509+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8> %v)
510+
// WEBASSEMBLY: ret
511+
}
512+
513+
i16x8 widen_high_u_i16x8_i8x16(i8x16 v) {
514+
return __builtin_wasm_widen_high_u_i16x8_i8x16(v);
515+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8> %v)
516+
// WEBASSEMBLY: ret
517+
}
518+
519+
i32x4 widen_low_s_i32x4_i16x8(i16x8 v) {
520+
return __builtin_wasm_widen_low_s_i32x4_i16x8(v);
521+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16> %v)
522+
// WEBASSEMBLY: ret
523+
}
524+
525+
i32x4 widen_high_s_i32x4_i16x8(i16x8 v) {
526+
return __builtin_wasm_widen_high_s_i32x4_i16x8(v);
527+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16> %v)
528+
// WEBASSEMBLY: ret
529+
}
530+
531+
i32x4 widen_low_u_i32x4_i16x8(i16x8 v) {
532+
return __builtin_wasm_widen_low_u_i32x4_i16x8(v);
533+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16> %v)
534+
// WEBASSEMBLY: ret
535+
}
536+
537+
i32x4 widen_high_u_i32x4_i16x8(i16x8 v) {
538+
return __builtin_wasm_widen_high_u_i32x4_i16x8(v);
539+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16> %v)
540+
// WEBASSEMBLY: ret
541+
}

‎llvm/include/llvm/IR/IntrinsicsWebAssembly.td

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,31 @@ def int_wasm_qfms :
117117
Intrinsic<[llvm_anyvector_ty],
118118
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
119119
[IntrNoMem, IntrSpeculatable]>;
120+
def int_wasm_narrow_signed :
121+
Intrinsic<[llvm_anyvector_ty],
122+
[llvm_anyvector_ty, LLVMMatchType<1>],
123+
[IntrNoMem, IntrSpeculatable]>;
124+
def int_wasm_narrow_unsigned :
125+
Intrinsic<[llvm_anyvector_ty],
126+
[llvm_anyvector_ty, LLVMMatchType<1>],
127+
[IntrNoMem, IntrSpeculatable]>;
128+
def int_wasm_widen_low_signed :
129+
Intrinsic<[llvm_anyvector_ty],
130+
[llvm_anyvector_ty],
131+
[IntrNoMem, IntrSpeculatable]>;
132+
def int_wasm_widen_high_signed :
133+
Intrinsic<[llvm_anyvector_ty],
134+
[llvm_anyvector_ty],
135+
[IntrNoMem, IntrSpeculatable]>;
136+
def int_wasm_widen_low_unsigned :
137+
Intrinsic<[llvm_anyvector_ty],
138+
[llvm_anyvector_ty],
139+
[IntrNoMem, IntrSpeculatable]>;
140+
def int_wasm_widen_high_unsigned :
141+
Intrinsic<[llvm_anyvector_ty],
142+
[llvm_anyvector_ty],
143+
[IntrNoMem, IntrSpeculatable]>;
144+
120145

121146
//===----------------------------------------------------------------------===//
122147
// Bulk memory intrinsics

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -712,6 +712,42 @@ defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
712712
defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
713713
defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
714714

715+
// Widening operations
716+
multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
717+
bits<32> baseInst> {
718+
defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_signed,
719+
vec#".widen_low_"#arg#"_s", baseInst>;
720+
defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_signed,
721+
vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>;
722+
defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_unsigned,
723+
vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>;
724+
defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_unsigned,
725+
vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>;
726+
}
727+
728+
defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 202>;
729+
defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 206>;
730+
731+
// Narrowing operations
732+
multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg,
733+
bits<32> baseInst> {
734+
defm NARROW_S_#vec_t :
735+
SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
736+
[(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed
737+
(arg_t V128:$low), (arg_t V128:$high))))],
738+
vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s",
739+
baseInst>;
740+
defm NARROW_U_#vec_t :
741+
SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
742+
[(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned
743+
(arg_t V128:$low), (arg_t V128:$high))))],
744+
vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u",
745+
!add(baseInst, 1)>;
746+
}
747+
748+
defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 198>;
749+
defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 200>;
750+
715751
// Lower llvm.wasm.trunc.saturate.* to saturating instructions
716752
def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
717753
(fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,30 @@ define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {
8787
ret <16 x i8> %a
8888
}
8989

90+
; CHECK-LABEL: narrow_signed_v16i8:
91+
; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
92+
; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
93+
; SIMD128-NEXT: return $pop[[R]]{{$}}
94+
declare <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(<8 x i16>, <8 x i16>)
95+
define <16 x i8> @narrow_signed_v16i8(<8 x i16> %low, <8 x i16> %high) {
96+
%a = call <16 x i8> @llvm.wasm.narrow.signed.v16i8.v8i16(
97+
<8 x i16> %low, <8 x i16> %high
98+
)
99+
ret <16 x i8> %a
100+
}
101+
102+
; CHECK-LABEL: narrow_unsigned_v16i8:
103+
; SIMD128-NEXT: .functype narrow_unsigned_v16i8 (v128, v128) -> (v128){{$}}
104+
; SIMD128-NEXT: i8x16.narrow_i16x8_u $push[[R:[0-9]+]]=, $0, $1{{$}}
105+
; SIMD128-NEXT: return $pop[[R]]{{$}}
106+
declare <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(<8 x i16>, <8 x i16>)
107+
define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
108+
%a = call <16 x i8> @llvm.wasm.narrow.unsigned.v16i8.v8i16(
109+
<8 x i16> %low, <8 x i16> %high
110+
)
111+
ret <16 x i8> %a
112+
}
113+
90114
; ==============================================================================
91115
; 8 x i16
92116
; ==============================================================================
@@ -166,6 +190,70 @@ define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {
166190
ret <8 x i16> %a
167191
}
168192

193+
; CHECK-LABEL: narrow_signed_v8i16:
194+
; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
195+
; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
196+
; SIMD128-NEXT: return $pop[[R]]{{$}}
197+
declare <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(<4 x i32>, <4 x i32>)
198+
define <8 x i16> @narrow_signed_v8i16(<4 x i32> %low, <4 x i32> %high) {
199+
%a = call <8 x i16> @llvm.wasm.narrow.signed.v8i16.v4i32(
200+
<4 x i32> %low, <4 x i32> %high
201+
)
202+
ret <8 x i16> %a
203+
}
204+
205+
; CHECK-LABEL: narrow_unsigned_v8i16:
206+
; SIMD128-NEXT: .functype narrow_unsigned_v8i16 (v128, v128) -> (v128){{$}}
207+
; SIMD128-NEXT: i16x8.narrow_i32x4_u $push[[R:[0-9]+]]=, $0, $1{{$}}
208+
; SIMD128-NEXT: return $pop[[R]]{{$}}
209+
declare <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(<4 x i32>, <4 x i32>)
210+
define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
211+
%a = call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(
212+
<4 x i32> %low, <4 x i32> %high
213+
)
214+
ret <8 x i16> %a
215+
}
216+
217+
; CHECK-LABEL: widen_low_signed_v8i16:
218+
; SIMD128-NEXT: .functype widen_low_signed_v8i16 (v128) -> (v128){{$}}
219+
; SIMD128-NEXT: i16x8.widen_low_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
220+
; SIMD128-NEXT: return $pop[[R]]{{$}}
221+
declare <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8>)
222+
define <8 x i16> @widen_low_signed_v8i16(<16 x i8> %v) {
223+
%a = call <8 x i16> @llvm.wasm.widen.low.signed.v8i16.v16i8(<16 x i8> %v)
224+
ret <8 x i16> %a
225+
}
226+
227+
; CHECK-LABEL: widen_high_signed_v8i16:
228+
; SIMD128-NEXT: .functype widen_high_signed_v8i16 (v128) -> (v128){{$}}
229+
; SIMD128-NEXT: i16x8.widen_high_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
230+
; SIMD128-NEXT: return $pop[[R]]{{$}}
231+
declare <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8>)
232+
define <8 x i16> @widen_high_signed_v8i16(<16 x i8> %v) {
233+
%a = call <8 x i16> @llvm.wasm.widen.high.signed.v8i16.v16i8(<16 x i8> %v)
234+
ret <8 x i16> %a
235+
}
236+
237+
; CHECK-LABEL: widen_low_unsigned_v8i16:
238+
; SIMD128-NEXT: .functype widen_low_unsigned_v8i16 (v128) -> (v128){{$}}
239+
; SIMD128-NEXT: i16x8.widen_low_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
240+
; SIMD128-NEXT: return $pop[[R]]{{$}}
241+
declare <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8>)
242+
define <8 x i16> @widen_low_unsigned_v8i16(<16 x i8> %v) {
243+
%a = call <8 x i16> @llvm.wasm.widen.low.unsigned.v8i16.v16i8(<16 x i8> %v)
244+
ret <8 x i16> %a
245+
}
246+
247+
; CHECK-LABEL: widen_high_unsigned_v8i16:
248+
; SIMD128-NEXT: .functype widen_high_unsigned_v8i16 (v128) -> (v128){{$}}
249+
; SIMD128-NEXT: i16x8.widen_high_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
250+
; SIMD128-NEXT: return $pop[[R]]{{$}}
251+
declare <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8>)
252+
define <8 x i16> @widen_high_unsigned_v8i16(<16 x i8> %v) {
253+
%a = call <8 x i16> @llvm.wasm.widen.high.unsigned.v8i16.v16i8(<16 x i8> %v)
254+
ret <8 x i16> %a
255+
}
256+
169257
; ==============================================================================
170258
; 4 x i32
171259
; ==============================================================================
@@ -223,6 +311,46 @@ define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
223311
ret <4 x i32> %a
224312
}
225313

314+
; CHECK-LABEL: widen_low_signed_v4i32:
315+
; SIMD128-NEXT: .functype widen_low_signed_v4i32 (v128) -> (v128){{$}}
316+
; SIMD128-NEXT: i32x4.widen_low_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
317+
; SIMD128-NEXT: return $pop[[R]]{{$}}
318+
declare <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16>)
319+
define <4 x i32> @widen_low_signed_v4i32(<8 x i16> %v) {
320+
%a = call <4 x i32> @llvm.wasm.widen.low.signed.v4i32.v8i16(<8 x i16> %v)
321+
ret <4 x i32> %a
322+
}
323+
324+
; CHECK-LABEL: widen_high_signed_v4i32:
325+
; SIMD128-NEXT: .functype widen_high_signed_v4i32 (v128) -> (v128){{$}}
326+
; SIMD128-NEXT: i32x4.widen_high_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
327+
; SIMD128-NEXT: return $pop[[R]]{{$}}
328+
declare <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16>)
329+
define <4 x i32> @widen_high_signed_v4i32(<8 x i16> %v) {
330+
%a = call <4 x i32> @llvm.wasm.widen.high.signed.v4i32.v8i16(<8 x i16> %v)
331+
ret <4 x i32> %a
332+
}
333+
334+
; CHECK-LABEL: widen_low_unsigned_v4i32:
335+
; SIMD128-NEXT: .functype widen_low_unsigned_v4i32 (v128) -> (v128){{$}}
336+
; SIMD128-NEXT: i32x4.widen_low_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
337+
; SIMD128-NEXT: return $pop[[R]]{{$}}
338+
declare <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16>)
339+
define <4 x i32> @widen_low_unsigned_v4i32(<8 x i16> %v) {
340+
%a = call <4 x i32> @llvm.wasm.widen.low.unsigned.v4i32.v8i16(<8 x i16> %v)
341+
ret <4 x i32> %a
342+
}
343+
344+
; CHECK-LABEL: widen_high_unsigned_v4i32:
345+
; SIMD128-NEXT: .functype widen_high_unsigned_v4i32 (v128) -> (v128){{$}}
346+
; SIMD128-NEXT: i32x4.widen_high_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
347+
; SIMD128-NEXT: return $pop[[R]]{{$}}
348+
declare <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16>)
349+
define <4 x i32> @widen_high_unsigned_v4i32(<8 x i16> %v) {
350+
%a = call <4 x i32> @llvm.wasm.widen.high.unsigned.v4i32.v8i16(<8 x i16> %v)
351+
ret <4 x i32> %a
352+
}
353+
226354
; ==============================================================================
227355
; 2 x i64
228356
; ==============================================================================

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