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[llvm][CodeGen] update live intervals for ModuloScheduleExpanderMVE (llvm#132677)
ModuloScheduleExpanderMVE and ModuloScheduleExpander are used sequentially in certain use cases. It is necessary to update live intervals for ModuloScheduleExpanderMVE; otherwise, crashes may occur.
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+266
-25
lines changed

2 files changed

+266
-25
lines changed

‎llvm/lib/CodeGen/ModuloSchedule.cpp

Lines changed: 44 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2137,7 +2137,8 @@ MachineInstr *ModuloScheduleExpanderMVE::cloneInstr(MachineInstr *OldMI) {
21372137
/// If it is already dedicated exit, return it. Otherwise, insert a new
21382138
/// block between them and return the new block.
21392139
static MachineBasicBlock *createDedicatedExit(MachineBasicBlock *Loop,
2140-
MachineBasicBlock *Exit) {
2140+
MachineBasicBlock *Exit,
2141+
LiveIntervals &LIS) {
21412142
if (Exit->pred_size() == 1)
21422143
return Exit;
21432144

@@ -2147,6 +2148,7 @@ static MachineBasicBlock *createDedicatedExit(MachineBasicBlock *Loop,
21472148
MachineBasicBlock *NewExit =
21482149
MF->CreateMachineBasicBlock(Loop->getBasicBlock());
21492150
MF->insert(Loop->getIterator(), NewExit);
2151+
LIS.insertMBBInMaps(NewExit);
21502152

21512153
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
21522154
SmallVector<MachineOperand, 4> Cond;
@@ -2282,12 +2284,17 @@ void ModuloScheduleExpanderMVE::generatePipelinedLoop() {
22822284
NewPreheader = MF.CreateMachineBasicBlock(OrigKernel->getBasicBlock());
22832285

22842286
MF.insert(OrigKernel->getIterator(), Check);
2287+
LIS.insertMBBInMaps(Check);
22852288
MF.insert(OrigKernel->getIterator(), Prolog);
2289+
LIS.insertMBBInMaps(Prolog);
22862290
MF.insert(OrigKernel->getIterator(), NewKernel);
2291+
LIS.insertMBBInMaps(NewKernel);
22872292
MF.insert(OrigKernel->getIterator(), Epilog);
2293+
LIS.insertMBBInMaps(Epilog);
22882294
MF.insert(OrigKernel->getIterator(), NewPreheader);
2295+
LIS.insertMBBInMaps(NewPreheader);
22892296

2290-
NewExit = createDedicatedExit(OrigKernel, OrigExit);
2297+
NewExit = createDedicatedExit(OrigKernel, OrigExit, LIS);
22912298

22922299
NewPreheader->transferSuccessorsAndUpdatePHIs(OrigPreheader);
22932300
TII->insertUnconditionalBranch(*NewPreheader, OrigKernel, DebugLoc());
@@ -2371,9 +2378,10 @@ void ModuloScheduleExpanderMVE::updateInstrUse(
23712378
UseMO.setReg(NewReg);
23722379
else {
23732380
Register SplitReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg));
2374-
BuildMI(*OrigKernel, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
2375-
SplitReg)
2376-
.addReg(NewReg);
2381+
MachineInstr *NewCopy = BuildMI(*OrigKernel, MI, MI->getDebugLoc(),
2382+
TII->get(TargetOpcode::COPY), SplitReg)
2383+
.addReg(NewReg);
2384+
LIS.InsertMachineInstrInMaps(*NewCopy);
23772385
UseMO.setReg(SplitReg);
23782386
}
23792387
}
@@ -2457,12 +2465,14 @@ void ModuloScheduleExpanderMVE::generatePhi(
24572465

24582466
assert(CorrespondReg.isValid());
24592467
Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg));
2460-
BuildMI(*NewKernel, NewKernel->getFirstNonPHI(), DebugLoc(),
2461-
TII->get(TargetOpcode::PHI), PhiReg)
2462-
.addReg(NewReg->second)
2463-
.addMBB(NewKernel)
2464-
.addReg(CorrespondReg)
2465-
.addMBB(Prolog);
2468+
MachineInstr *NewPhi =
2469+
BuildMI(*NewKernel, NewKernel->getFirstNonPHI(), DebugLoc(),
2470+
TII->get(TargetOpcode::PHI), PhiReg)
2471+
.addReg(NewReg->second)
2472+
.addMBB(NewKernel)
2473+
.addReg(CorrespondReg)
2474+
.addMBB(Prolog);
2475+
LIS.InsertMachineInstrInMaps(*NewPhi);
24662476
PhiVRMap[UnrollNum][OrigReg] = PhiReg;
24672477
}
24682478
}
@@ -2500,18 +2510,22 @@ void ModuloScheduleExpanderMVE::mergeRegUsesAfterPipeline(Register OrigReg,
25002510
// remaining iterations) with the route that execute the original loop.
25012511
if (!UsesAfterLoop.empty()) {
25022512
Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg));
2503-
BuildMI(*NewExit, NewExit->getFirstNonPHI(), DebugLoc(),
2504-
TII->get(TargetOpcode::PHI), PhiReg)
2505-
.addReg(OrigReg)
2506-
.addMBB(OrigKernel)
2507-
.addReg(NewReg)
2508-
.addMBB(Epilog);
2513+
MachineInstr *NewPhi =
2514+
BuildMI(*NewExit, NewExit->getFirstNonPHI(), DebugLoc(),
2515+
TII->get(TargetOpcode::PHI), PhiReg)
2516+
.addReg(OrigReg)
2517+
.addMBB(OrigKernel)
2518+
.addReg(NewReg)
2519+
.addMBB(Epilog);
2520+
LIS.InsertMachineInstrInMaps(*NewPhi);
25092521

25102522
for (MachineOperand *MO : UsesAfterLoop)
25112523
MO->setReg(PhiReg);
25122524

2513-
if (!LIS.hasInterval(PhiReg))
2514-
LIS.createEmptyInterval(PhiReg);
2525+
// The interval of OrigReg is invalid and should be recalculated when
2526+
// LiveInterval::getInterval() is called.
2527+
if (LIS.hasInterval(OrigReg))
2528+
LIS.removeInterval(OrigReg);
25152529
}
25162530

25172531
// Merge routes from the pipelined loop and the bypassed route before the
@@ -2521,12 +2535,14 @@ void ModuloScheduleExpanderMVE::mergeRegUsesAfterPipeline(Register OrigReg,
25212535
Register InitReg, LoopReg;
25222536
getPhiRegs(*Phi, OrigKernel, InitReg, LoopReg);
25232537
Register NewInit = MRI.createVirtualRegister(MRI.getRegClass(InitReg));
2524-
BuildMI(*NewPreheader, NewPreheader->getFirstNonPHI(), Phi->getDebugLoc(),
2525-
TII->get(TargetOpcode::PHI), NewInit)
2526-
.addReg(InitReg)
2527-
.addMBB(Check)
2528-
.addReg(NewReg)
2529-
.addMBB(Epilog);
2538+
MachineInstr *NewPhi =
2539+
BuildMI(*NewPreheader, NewPreheader->getFirstNonPHI(),
2540+
Phi->getDebugLoc(), TII->get(TargetOpcode::PHI), NewInit)
2541+
.addReg(InitReg)
2542+
.addMBB(Check)
2543+
.addReg(NewReg)
2544+
.addMBB(Epilog);
2545+
LIS.InsertMachineInstrInMaps(*NewPhi);
25302546
replacePhiSrc(*Phi, InitReg, NewInit, NewPreheader);
25312547
}
25322548
}
@@ -2549,6 +2565,7 @@ void ModuloScheduleExpanderMVE::generateProlog(
25492565
updateInstrDef(NewMI, PrologVRMap[PrologNum], false);
25502566
NewMIMap[NewMI] = {PrologNum, StageNum};
25512567
Prolog->push_back(NewMI);
2568+
LIS.InsertMachineInstrInMaps(*NewMI);
25522569
}
25532570
}
25542571

@@ -2587,6 +2604,7 @@ void ModuloScheduleExpanderMVE::generateKernel(
25872604
generatePhi(MI, UnrollNum, PrologVRMap, KernelVRMap, PhiVRMap);
25882605
NewMIMap[NewMI] = {UnrollNum, StageNum};
25892606
NewKernel->push_back(NewMI);
2607+
LIS.InsertMachineInstrInMaps(*NewMI);
25902608
}
25912609
}
25922610

@@ -2625,6 +2643,7 @@ void ModuloScheduleExpanderMVE::generateEpilog(
26252643
updateInstrDef(NewMI, EpilogVRMap[EpilogNum], StageNum - 1 == EpilogNum);
26262644
NewMIMap[NewMI] = {EpilogNum, StageNum};
26272645
Epilog->push_back(NewMI);
2646+
LIS.InsertMachineInstrInMaps(*NewMI);
26282647
}
26292648
}
26302649

‎llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir

Lines changed: 222 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,222 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc --mtriple=aarch64 %s -run-pass=pipeliner -pipeliner-mve-cg -o -| FileCheck %s
3+
4+
...
5+
---
6+
name: foo
7+
tracksRegLiveness: true
8+
body: |
9+
; CHECK-LABEL: name: foo
10+
; CHECK: bb.0:
11+
; CHECK-NEXT: successors: %bb.13(0x80000000)
12+
; CHECK-NEXT: liveins: $x0
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
15+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $xzr
16+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[COPY1]]
17+
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
18+
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
19+
; CHECK-NEXT: {{ $}}
20+
; CHECK-NEXT: bb.13:
21+
; CHECK-NEXT: successors: %bb.14(0x80000000), %bb.15(0x00000000)
22+
; CHECK-NEXT: {{ $}}
23+
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0
24+
; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = nsw SUBSXri [[SUBREG_TO_REG]], 1, 0, implicit-def $nzcv
25+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64all = COPY [[SUBSXri]]
26+
; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
27+
; CHECK-NEXT: Bcc 0, %bb.15, implicit $nzcv
28+
; CHECK-NEXT: B %bb.14
29+
; CHECK-NEXT: {{ $}}
30+
; CHECK-NEXT: bb.14:
31+
; CHECK-NEXT: successors: %bb.15(0x04000000), %bb.14(0x7c000000)
32+
; CHECK-NEXT: {{ $}}
33+
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY3]], %bb.13, %73, %bb.14
34+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr64 = PHI [[SUBREG_TO_REG1]], %bb.13, %72, %bb.14
35+
; CHECK-NEXT: [[PHI2:%[0-9]+]]:fpr64 = PHI [[LDRDui]], %bb.13, %70, %bb.14
36+
; CHECK-NEXT: STRDui [[PHI2]], [[COPY]], 0
37+
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0
38+
; CHECK-NEXT: [[SUBSXri1:%[0-9]+]]:gpr64 = nsw SUBSXri [[PHI]], 1, 0, implicit-def $nzcv
39+
; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
40+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64all = COPY [[SUBSXri1]]
41+
; CHECK-NEXT: Bcc 1, %bb.14, implicit $nzcv
42+
; CHECK-NEXT: B %bb.15
43+
; CHECK-NEXT: {{ $}}
44+
; CHECK-NEXT: bb.15:
45+
; CHECK-NEXT: successors: %bb.2(0x80000000)
46+
; CHECK-NEXT: {{ $}}
47+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:gpr64 = PHI [[COPY2]], %bb.13, [[PHI1]], %bb.14
48+
; CHECK-NEXT: [[PHI4:%[0-9]+]]:fpr64 = PHI [[LDRDui]], %bb.13, [[LDRDui1]], %bb.14
49+
; CHECK-NEXT: STRDui [[PHI4]], [[COPY]], 0
50+
; CHECK-NEXT: B %bb.2
51+
; CHECK-NEXT: {{ $}}
52+
; CHECK-NEXT: bb.2:
53+
; CHECK-NEXT: successors: %bb.3(0x80000000)
54+
; CHECK-NEXT: {{ $}}
55+
; CHECK-NEXT: bb.3:
56+
; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: CBNZX [[PHI3]], %bb.3
59+
; CHECK-NEXT: B %bb.4
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: bb.4:
62+
; CHECK-NEXT: successors: %bb.5(0x80000000)
63+
; CHECK-NEXT: {{ $}}
64+
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
65+
; CHECK-NEXT: {{ $}}
66+
; CHECK-NEXT: bb.5:
67+
; CHECK-NEXT: successors: %bb.7(0x80000000)
68+
; CHECK-NEXT: {{ $}}
69+
; CHECK-NEXT: [[PHI5:%[0-9]+]]:fpr64 = PHI [[FMOVD0_]], %bb.4, %62, %bb.12
70+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr64all = COPY $xzr
71+
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr64common = COPY [[COPY5]]
72+
; CHECK-NEXT: B %bb.7
73+
; CHECK-NEXT: {{ $}}
74+
; CHECK-NEXT: bb.7:
75+
; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.11(0x40000000)
76+
; CHECK-NEXT: {{ $}}
77+
; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64common = ADDSXri [[COPY6]], 1, 0, implicit-def $nzcv
78+
; CHECK-NEXT: [[CSINCXr:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 3, implicit $nzcv
79+
; CHECK-NEXT: [[ADDSXri1:%[0-9]+]]:gpr64common = ADDSXri [[ADDSXri]], 1, 0, implicit-def $nzcv
80+
; CHECK-NEXT: [[CSINCXr1:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr]], [[CSINCXr]], 3, implicit $nzcv
81+
; CHECK-NEXT: [[ADDSXri2:%[0-9]+]]:gpr64common = ADDSXri [[ADDSXri1]], 1, 0, implicit-def $nzcv
82+
; CHECK-NEXT: [[CSINCXr2:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr1]], [[CSINCXr1]], 3, implicit $nzcv
83+
; CHECK-NEXT: [[ADDSXri3:%[0-9]+]]:gpr64 = ADDSXri [[ADDSXri2]], 1, 0, implicit-def $nzcv
84+
; CHECK-NEXT: [[CSINCXr3:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr2]], [[CSINCXr2]], 3, implicit $nzcv
85+
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr3]], 0, 0, implicit-def $nzcv
86+
; CHECK-NEXT: Bcc 0, %bb.8, implicit $nzcv
87+
; CHECK-NEXT: B %bb.11
88+
; CHECK-NEXT: {{ $}}
89+
; CHECK-NEXT: bb.8:
90+
; CHECK-NEXT: successors: %bb.9(0x80000000)
91+
; CHECK-NEXT: {{ $}}
92+
; CHECK-NEXT: [[ADDSXri4:%[0-9]+]]:gpr64 = ADDSXri [[COPY6]], 1, 0, implicit-def $nzcv
93+
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY6]], 61, 60
94+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr64common = COPY [[ADDSXri4]]
95+
; CHECK-NEXT: [[LDRDui2:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri]], 1
96+
; CHECK-NEXT: [[ADDSXri5:%[0-9]+]]:gpr64 = ADDSXri [[COPY7]], 1, 0, implicit-def $nzcv
97+
; CHECK-NEXT: [[UBFMXri1:%[0-9]+]]:gpr64common = UBFMXri [[COPY7]], 61, 60
98+
; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr64all = COPY [[ADDSXri5]]
99+
; CHECK-NEXT: {{ $}}
100+
; CHECK-NEXT: bb.9:
101+
; CHECK-NEXT: successors: %bb.9(0x40000000), %bb.10(0x40000000)
102+
; CHECK-NEXT: {{ $}}
103+
; CHECK-NEXT: [[PHI6:%[0-9]+]]:gpr64 = PHI %38, %bb.9, [[ADDSXri4]], %bb.8
104+
; CHECK-NEXT: [[PHI7:%[0-9]+]]:gpr64common = PHI %40, %bb.9, [[UBFMXri]], %bb.8
105+
; CHECK-NEXT: [[PHI8:%[0-9]+]]:gpr64all = PHI %43, %bb.9, [[COPY7]], %bb.8
106+
; CHECK-NEXT: [[PHI9:%[0-9]+]]:fpr64 = PHI %45, %bb.9, [[LDRDui2]], %bb.8
107+
; CHECK-NEXT: [[PHI10:%[0-9]+]]:gpr64 = PHI %47, %bb.9, [[ADDSXri5]], %bb.8
108+
; CHECK-NEXT: [[PHI11:%[0-9]+]]:gpr64common = PHI %49, %bb.9, [[UBFMXri1]], %bb.8
109+
; CHECK-NEXT: [[PHI12:%[0-9]+]]:fpr64 = PHI %51, %bb.9, [[PHI5]], %bb.8
110+
; CHECK-NEXT: [[PHI13:%[0-9]+]]:gpr64common = PHI %53, %bb.9, [[COPY8]], %bb.8
111+
; CHECK-NEXT: [[LDRDui3:%[0-9]+]]:fpr64 = LDRDui [[PHI11]], 1
112+
; CHECK-NEXT: [[ADDSXri6:%[0-9]+]]:gpr64 = ADDSXri [[PHI13]], 1, 0, implicit-def $nzcv
113+
; CHECK-NEXT: [[UBFMXri2:%[0-9]+]]:gpr64common = UBFMXri [[PHI13]], 61, 60
114+
; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI12]], [[PHI9]], implicit $fpcr
115+
; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr64common = COPY [[ADDSXri6]]
116+
; CHECK-NEXT: [[LDRDui4:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri2]], 1
117+
; CHECK-NEXT: [[ADDSXri7:%[0-9]+]]:gpr64common = ADDSXri [[COPY9]], 1, 0, implicit-def $nzcv
118+
; CHECK-NEXT: [[UBFMXri3:%[0-9]+]]:gpr64common = UBFMXri [[COPY9]], 61, 60
119+
; CHECK-NEXT: [[FADDDrr1:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr]], [[LDRDui3]], implicit $fpcr
120+
; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr64all = COPY [[ADDSXri7]]
121+
; CHECK-NEXT: [[CSINCXr4:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 3, implicit $nzcv
122+
; CHECK-NEXT: [[ADDSXri8:%[0-9]+]]:gpr64 = ADDSXri [[ADDSXri7]], 1, 0, implicit-def $nzcv
123+
; CHECK-NEXT: [[CSINCXr5:%[0-9]+]]:gpr64common = CSINCXr [[CSINCXr4]], [[CSINCXr4]], 3, implicit $nzcv
124+
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr5]], 0, 0, implicit-def $nzcv
125+
; CHECK-NEXT: Bcc 0, %bb.9, implicit $nzcv
126+
; CHECK-NEXT: B %bb.10
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: bb.10:
129+
; CHECK-NEXT: successors: %bb.11(0x40000000), %bb.12(0x40000000)
130+
; CHECK-NEXT: {{ $}}
131+
; CHECK-NEXT: [[LDRDui5:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri3]], 1
132+
; CHECK-NEXT: [[FADDDrr2:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr1]], [[LDRDui4]], implicit $fpcr
133+
; CHECK-NEXT: [[FADDDrr3:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[FADDDrr2]], [[LDRDui5]], implicit $fpcr
134+
; CHECK-NEXT: [[ADDSXri9:%[0-9]+]]:gpr64 = ADDSXri [[COPY9]], 1, 0, implicit-def $nzcv
135+
; CHECK-NEXT: [[CSINCXr6:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 3, implicit $nzcv
136+
; CHECK-NEXT: dead $xzr = SUBSXri [[CSINCXr6]], 0, 0, implicit-def $nzcv
137+
; CHECK-NEXT: Bcc 0, %bb.11, implicit $nzcv
138+
; CHECK-NEXT: B %bb.12
139+
; CHECK-NEXT: {{ $}}
140+
; CHECK-NEXT: bb.11:
141+
; CHECK-NEXT: successors: %bb.6(0x80000000)
142+
; CHECK-NEXT: {{ $}}
143+
; CHECK-NEXT: [[PHI14:%[0-9]+]]:gpr64common = PHI [[COPY6]], %bb.7, [[COPY10]], %bb.10
144+
; CHECK-NEXT: [[PHI15:%[0-9]+]]:fpr64 = PHI [[PHI5]], %bb.7, [[FADDDrr3]], %bb.10
145+
; CHECK-NEXT: B %bb.6
146+
; CHECK-NEXT: {{ $}}
147+
; CHECK-NEXT: bb.12:
148+
; CHECK-NEXT: successors: %bb.5(0x80000000)
149+
; CHECK-NEXT: {{ $}}
150+
; CHECK-NEXT: [[PHI16:%[0-9]+]]:fpr64 = PHI %13, %bb.6, [[FADDDrr3]], %bb.10
151+
; CHECK-NEXT: B %bb.5
152+
; CHECK-NEXT: {{ $}}
153+
; CHECK-NEXT: bb.6:
154+
; CHECK-NEXT: successors: %bb.12(0x04000000), %bb.6(0x7c000000)
155+
; CHECK-NEXT: {{ $}}
156+
; CHECK-NEXT: [[PHI17:%[0-9]+]]:gpr64common = PHI [[PHI14]], %bb.11, %17, %bb.6
157+
; CHECK-NEXT: [[PHI18:%[0-9]+]]:fpr64 = PHI [[PHI15]], %bb.11, %13, %bb.6
158+
; CHECK-NEXT: [[UBFMXri4:%[0-9]+]]:gpr64common = UBFMXri [[PHI17]], 61, 60
159+
; CHECK-NEXT: [[LDRDui6:%[0-9]+]]:fpr64 = LDRDui [[UBFMXri4]], 1
160+
; CHECK-NEXT: [[FADDDrr4:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[PHI18]], [[LDRDui6]], implicit $fpcr
161+
; CHECK-NEXT: [[ADDSXri10:%[0-9]+]]:gpr64 = ADDSXri [[PHI17]], 1, 0, implicit-def $nzcv
162+
; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr64all = COPY [[ADDSXri10]]
163+
; CHECK-NEXT: Bcc 2, %bb.12, implicit $nzcv
164+
; CHECK-NEXT: B %bb.6
165+
bb.0:
166+
successors: %bb.1(0x80000000)
167+
liveins: $x0
168+
169+
%0:gpr64common = COPY $x0
170+
%1:gpr64sp = COPY $xzr
171+
%2:gpr64all = COPY %1
172+
%3:gpr32 = MOVi32imm 1
173+
%4:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32
174+
175+
bb.1:
176+
successors: %bb.2(0x04000000), %bb.1(0x7c000000)
177+
178+
%5:gpr64sp = PHI %4, %bb.0, %6, %bb.1
179+
%7:gpr64 = PHI %2, %bb.0, %8, %bb.1
180+
%9:fpr64 = LDRDui %1, 0
181+
STRDui killed %9, %0, 0
182+
%10:gpr64 = nsw SUBSXri %5, 1, 0, implicit-def $nzcv
183+
%6:gpr64all = COPY %10
184+
%8:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32
185+
Bcc 1, %bb.1, implicit $nzcv
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B %bb.2
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bb.2:
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successors: %bb.3(0x80000000)
190+
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bb.3:
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successors: %bb.4(0x04000000), %bb.3(0x7c000000)
193+
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CBNZX %7, %bb.3
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B %bb.4
196+
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bb.4:
198+
successors: %bb.5(0x80000000)
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200+
%11:fpr64 = FMOVD0
201+
202+
bb.5:
203+
successors: %bb.6(0x80000000)
204+
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%12:fpr64 = PHI %11, %bb.4, %13, %bb.6
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%14:gpr64all = COPY $xzr
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%15:gpr64all = COPY %14
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bb.6:
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successors: %bb.5(0x04000000), %bb.6(0x7c000000)
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%16:gpr64common = PHI %15, %bb.5, %17, %bb.6
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%18:fpr64 = PHI %12, %bb.5, %13, %bb.6
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%19:gpr64common = UBFMXri %16, 61, 60
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%20:fpr64 = LDRDui killed %19, 1
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%13:fpr64 = nofpexcept FADDDrr %18, killed %20, implicit $fpcr
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%21:gpr64 = ADDSXri %16, 1, 0, implicit-def $nzcv
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%17:gpr64all = COPY %21
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Bcc 2, %bb.5, implicit $nzcv
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B %bb.6
221+
222+
...

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