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Merge commit 'a18818207ab5' from llvm.org/master into apple/master
2 parents 7f92888 + a188182 commit b428916

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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10735,16 +10735,16 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
1073510735
// e.g. trunc (i64 (bitcast v2i32:x)) -> extract_vector_elt v2i32:x, idx
1073610736
if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
1073710737
SDValue VecSrc = N0.getOperand(0);
10738-
EVT SrcVT = VecSrc.getValueType();
10739-
if (SrcVT.isVector() && SrcVT.getScalarType() == VT &&
10738+
EVT VecSrcVT = VecSrc.getValueType();
10739+
if (VecSrcVT.isVector() && VecSrcVT.getScalarType() == VT &&
1074010740
(!LegalOperations ||
10741-
TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, SrcVT))) {
10741+
TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecSrcVT))) {
1074210742
SDLoc SL(N);
1074310743

1074410744
EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
10745-
unsigned Idx = isLE ? 0 : SrcVT.getVectorNumElements() - 1;
10746-
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT,
10747-
VecSrc, DAG.getConstant(Idx, SL, IdxVT));
10745+
unsigned Idx = isLE ? 0 : VecSrcVT.getVectorNumElements() - 1;
10746+
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT, VecSrc,
10747+
DAG.getConstant(Idx, SL, IdxVT));
1074810748
}
1074910749
}
1075010750

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