Skip to content

Commit b9d96ce

Browse files
davemgreendavemgreen
committed
[ARM] MVE integer compares and selects
This adds the very basics for MVE vector predication, adding integer VCMP and VSEL instruction support. This is done through predicate registers (MVT::v16i1, MVT::v8i1, MVT::v4i1), but otherwise using same mechanics as NEON to custom lower setcc's through ARMISD::VCXX nodes (VCEQ, VCGT, VCEQZ, etc). An extra VCNE was added, as this can be handled sensibly by MVE's expanded number of VCMP condition codes. (There are also VCLE and VCLT which are added later). VPSEL is also added here, simply selecting on the vselect. Original code by David Sherwood. Differential Revision: https://reviews.llvm.org/D65051 llvm-svn: 366885
1 parent d22f877 commit b9d96ce

File tree

8 files changed

+1058
-40
lines changed

8 files changed

+1058
-40
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 48 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,7 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
258258
setOperationAction(ISD::UMIN, VT, Legal);
259259
setOperationAction(ISD::UMAX, VT, Legal);
260260
setOperationAction(ISD::ABS, VT, Legal);
261+
setOperationAction(ISD::SETCC, VT, Custom);
261262

262263
// No native support for these.
263264
setOperationAction(ISD::UDIV, VT, Expand);
@@ -334,6 +335,12 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
334335
setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
335336
setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
336337
setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
338+
339+
// Predicate types
340+
const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
341+
for (auto VT : pTypes) {
342+
addRegisterClass(VT, &ARM::VCCRRegClass);
343+
}
337344
}
338345

339346
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
@@ -1500,6 +1507,8 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
15001507

15011508
case ARMISD::VCEQ: return "ARMISD::VCEQ";
15021509
case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1510+
case ARMISD::VCNE: return "ARMISD::VCNE";
1511+
case ARMISD::VCNEZ: return "ARMISD::VCNEZ";
15031512
case ARMISD::VCGE: return "ARMISD::VCGE";
15041513
case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
15051514
case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
@@ -1601,6 +1610,11 @@ EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
16011610
EVT VT) const {
16021611
if (!VT.isVector())
16031612
return getPointerTy(DL);
1613+
1614+
// MVE has a predicate register.
1615+
if (Subtarget->hasMVEIntegerOps() &&
1616+
(VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1617+
return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
16041618
return VT.changeVectorElementTypeToInteger();
16051619
}
16061620

@@ -5849,7 +5863,8 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
58495863
return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
58505864
}
58515865

5852-
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5866+
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG,
5867+
const ARMSubtarget *ST) {
58535868
SDValue TmpOp0, TmpOp1;
58545869
bool Invert = false;
58555870
bool Swap = false;
@@ -5858,11 +5873,23 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
58585873
SDValue Op0 = Op.getOperand(0);
58595874
SDValue Op1 = Op.getOperand(1);
58605875
SDValue CC = Op.getOperand(2);
5861-
EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
58625876
EVT VT = Op.getValueType();
58635877
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
58645878
SDLoc dl(Op);
58655879

5880+
EVT CmpVT;
5881+
if (ST->hasNEON())
5882+
CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5883+
else {
5884+
assert(ST->hasMVEIntegerOps() &&
5885+
"No hardware support for integer vector comparison!");
5886+
5887+
if (Op.getValueType().getVectorElementType() != MVT::i1)
5888+
return SDValue();
5889+
5890+
CmpVT = VT;
5891+
}
5892+
58665893
if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
58675894
(SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
58685895
// Special-case integer 64-bit equality comparisons. They aren't legal,
@@ -5930,7 +5957,12 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
59305957
// Integer comparisons.
59315958
switch (SetCCOpcode) {
59325959
default: llvm_unreachable("Illegal integer comparison");
5933-
case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH;
5960+
case ISD::SETNE:
5961+
if (ST->hasMVEIntegerOps()) {
5962+
Opc = ARMISD::VCNE; break;
5963+
} else {
5964+
Invert = true; LLVM_FALLTHROUGH;
5965+
}
59345966
case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
59355967
case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
59365968
case ISD::SETGT: Opc = ARMISD::VCGT; break;
@@ -5943,7 +5975,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
59435975
}
59445976

59455977
// Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5946-
if (Opc == ARMISD::VCEQ) {
5978+
if (ST->hasNEON() && Opc == ARMISD::VCEQ) {
59475979
SDValue AndOp;
59485980
if (ISD::isBuildVectorAllZeros(Op1.getNode()))
59495981
AndOp = Op0;
@@ -5982,6 +6014,9 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
59826014
SDValue Result;
59836015
if (SingleOp.getNode()) {
59846016
switch (Opc) {
6017+
case ARMISD::VCNE:
6018+
assert(ST->hasMVEIntegerOps() && "Unexpected DAG node");
6019+
Result = DAG.getNode(ARMISD::VCNEZ, dl, CmpVT, SingleOp); break;
59856020
case ARMISD::VCEQ:
59866021
Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
59876022
case ARMISD::VCGE:
@@ -8436,7 +8471,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
84368471
case ISD::CTTZ:
84378472
case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
84388473
case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
8439-
case ISD::SETCC: return LowerVSETCC(Op, DAG);
8474+
case ISD::SETCC: return LowerVSETCC(Op, DAG, Subtarget);
84408475
case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG);
84418476
case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
84428477
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
@@ -13594,6 +13629,14 @@ bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned,
1359413629

1359513630
if (!Subtarget->hasMVEIntegerOps())
1359613631
return false;
13632+
13633+
// These are for predicates
13634+
if ((Ty == MVT::v16i1 || Ty == MVT::v8i1 || Ty == MVT::v4i1)) {
13635+
if (Fast)
13636+
*Fast = true;
13637+
return true;
13638+
}
13639+
1359713640
if (Ty != MVT::v16i8 && Ty != MVT::v8i16 && Ty != MVT::v8f16 &&
1359813641
Ty != MVT::v4i32 && Ty != MVT::v4f32 && Ty != MVT::v2i64 &&
1359913642
Ty != MVT::v2f64 &&

‎llvm/lib/Target/ARM/ARMISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,8 @@ class VectorType;
131131

132132
VCEQ, // Vector compare equal.
133133
VCEQZ, // Vector compare equal to zero.
134+
VCNE, // Vector compare not equal (MVE)
135+
VCNEZ, // Vector compare not equal to zero (MVE)
134136
VCGE, // Vector compare greater than or equal.
135137
VCGEZ, // Vector compare greater than or equal to zero.
136138
VCLEZ, // Vector compare less than or equal to zero.

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -265,9 +265,26 @@ def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>;
265265
def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>;
266266
def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>;
267267

268+
def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
269+
def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
270+
271+
def ARMvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
272+
def ARMvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
273+
def ARMvcne : SDNode<"ARMISD::VCNE", SDTARMVCMP>;
274+
def ARMvcnez : SDNode<"ARMISD::VCNEZ", SDTARMVCMPZ>;
275+
def ARMvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
276+
def ARMvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
277+
def ARMvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
278+
def ARMvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
279+
def ARMvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
280+
def ARMvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
281+
def ARMvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
282+
def ARMvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
283+
268284
def ARMWLS : SDNode<"ARMISD::WLS", SDT_ARMLoLoop, [SDNPHasChain]>;
269285
def ARMLE : SDNode<"ARMISD::LE", SDT_ARMLoLoop, [SDNPHasChain]>;
270286
def ARMLoopDec : SDNode<"ARMISD::LOOP_DEC", SDTIntBinOp, [SDNPHasChain]>;
287+
271288
//===----------------------------------------------------------------------===//
272289
// ARM Flag Definitions.
273290

‎llvm/lib/Target/ARM/ARMInstrMVE.td

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2982,6 +2982,40 @@ def MVE_VCMPs8r : MVE_VCMPqrs<"s8", 0b00>;
29822982
def MVE_VCMPs16r : MVE_VCMPqrs<"s16", 0b01>;
29832983
def MVE_VCMPs32r : MVE_VCMPqrs<"s32", 0b10>;
29842984

2985+
multiclass unpred_vcmp_z<SDPatternOperator opnode, string suffix, int fc> {
2986+
def i8 : Pat<(v16i1 (opnode (v16i8 MQPR:$v1))),
2987+
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc))>;
2988+
def i16 : Pat<(v8i1 (opnode (v8i16 MQPR:$v1))),
2989+
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc))>;
2990+
def i32 : Pat<(v4i1 (opnode (v4i32 MQPR:$v1))),
2991+
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc))>;
2992+
}
2993+
2994+
multiclass unpred_vcmp_r<SDPatternOperator opnode, string suffix, int fc> {
2995+
def i8 : Pat<(v16i1 (opnode (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
2996+
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc))>;
2997+
def i16 : Pat<(v8i1 (opnode (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
2998+
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc))>;
2999+
def i32 : Pat<(v4i1 (opnode (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
3000+
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc))>;
3001+
}
3002+
3003+
let Predicates = [HasMVEInt] in {
3004+
defm MVE_VCEQZ : unpred_vcmp_z<ARMvceqz, "i", 0>;
3005+
defm MVE_VCNEZ : unpred_vcmp_z<ARMvcnez, "i", 1>;
3006+
defm MVE_VCLEZ : unpred_vcmp_z<ARMvclez, "s", 13>;
3007+
defm MVE_VCGTZ : unpred_vcmp_z<ARMvcgtz, "s", 12>;
3008+
defm MVE_VCLTZ : unpred_vcmp_z<ARMvcltz, "s", 11>;
3009+
defm MVE_VCGEZ : unpred_vcmp_z<ARMvcgez, "s", 10>;
3010+
3011+
defm MVE_VCEQ : unpred_vcmp_r<ARMvceq, "i", 0>;
3012+
defm MVE_VCNE : unpred_vcmp_r<ARMvcne, "i", 1>;
3013+
defm MVE_VCGT : unpred_vcmp_r<ARMvcgt, "s", 12>;
3014+
defm MVE_VCGE : unpred_vcmp_r<ARMvcge, "s", 10>;
3015+
defm MVE_VCGTU : unpred_vcmp_r<ARMvcgtu, "u", 8>;
3016+
defm MVE_VCGEU : unpred_vcmp_r<ARMvcgeu, "u", 2>;
3017+
}
3018+
29853019
// end of MVE compares
29863020

29873021
// start of MVE_qDest_qSrc
@@ -4369,6 +4403,15 @@ foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32",
43694403
def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm",
43704404
(MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
43714405

4406+
let Predicates = [HasMVEInt] in {
4407+
def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
4408+
(v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0, VCCR:$pred))>;
4409+
def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
4410+
(v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0, VCCR:$pred))>;
4411+
def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
4412+
(v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0, VCCR:$pred))>;
4413+
}
4414+
43724415
def MVE_VPNOT : MVE_p<(outs), (ins), NoItinerary,
43734416
"vpnot", "", "", vpred_n, "", []> {
43744417
let Inst{31-0} = 0b11111110001100010000111101001101;

‎llvm/lib/Target/ARM/ARMInstrNEON.td

Lines changed: 22 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -478,19 +478,6 @@ def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
478478
// NEON-specific DAG Nodes.
479479
//===----------------------------------------------------------------------===//
480480

481-
def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
482-
def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
483-
484-
def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
485-
def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
486-
def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
487-
def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
488-
def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
489-
def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
490-
def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
491-
def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
492-
def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
493-
def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
494481
def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
495482

496483
// Types for vector shift by immediates. The "SHX" version is for long and
@@ -5027,66 +5014,66 @@ def : Pat<(v2i32 (trunc (ARMvshruImm (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
50275014

50285015
// VCEQ : Vector Compare Equal
50295016
defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5030-
IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
5017+
IIC_VSUBi4Q, "vceq", "i", ARMvceq, 1>;
50315018
def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
5032-
NEONvceq, 1>;
5019+
ARMvceq, 1>;
50335020
def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
5034-
NEONvceq, 1>;
5021+
ARMvceq, 1>;
50355022
def VCEQhd : N3VD<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16,
5036-
NEONvceq, 1>,
5023+
ARMvceq, 1>,
50375024
Requires<[HasNEON, HasFullFP16]>;
50385025
def VCEQhq : N3VQ<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16,
5039-
NEONvceq, 1>,
5026+
ARMvceq, 1>,
50405027
Requires<[HasNEON, HasFullFP16]>;
50415028

50425029
let TwoOperandAliasConstraint = "$Vm = $Vd" in
50435030
defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
5044-
"$Vd, $Vm, #0", NEONvceqz>;
5031+
"$Vd, $Vm, #0", ARMvceqz>;
50455032

50465033
// VCGE : Vector Compare Greater Than or Equal
50475034
defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5048-
IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
5035+
IIC_VSUBi4Q, "vcge", "s", ARMvcge, 0>;
50495036
defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5050-
IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
5037+
IIC_VSUBi4Q, "vcge", "u", ARMvcgeu, 0>;
50515038
def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
5052-
NEONvcge, 0>;
5039+
ARMvcge, 0>;
50535040
def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
5054-
NEONvcge, 0>;
5041+
ARMvcge, 0>;
50555042
def VCGEhd : N3VD<1,0,0b01,0b1110,0, IIC_VBIND, "vcge", "f16", v4i16, v4f16,
5056-
NEONvcge, 0>,
5043+
ARMvcge, 0>,
50575044
Requires<[HasNEON, HasFullFP16]>;
50585045
def VCGEhq : N3VQ<1,0,0b01,0b1110,0, IIC_VBINQ, "vcge", "f16", v8i16, v8f16,
5059-
NEONvcge, 0>,
5046+
ARMvcge, 0>,
50605047
Requires<[HasNEON, HasFullFP16]>;
50615048

50625049
let TwoOperandAliasConstraint = "$Vm = $Vd" in {
50635050
defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
5064-
"$Vd, $Vm, #0", NEONvcgez>;
5051+
"$Vd, $Vm, #0", ARMvcgez>;
50655052
defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
5066-
"$Vd, $Vm, #0", NEONvclez>;
5053+
"$Vd, $Vm, #0", ARMvclez>;
50675054
}
50685055

50695056
// VCGT : Vector Compare Greater Than
50705057
defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5071-
IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
5058+
IIC_VSUBi4Q, "vcgt", "s", ARMvcgt, 0>;
50725059
defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
5073-
IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
5060+
IIC_VSUBi4Q, "vcgt", "u", ARMvcgtu, 0>;
50745061
def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
5075-
NEONvcgt, 0>;
5062+
ARMvcgt, 0>;
50765063
def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
5077-
NEONvcgt, 0>;
5064+
ARMvcgt, 0>;
50785065
def VCGThd : N3VD<1,0,0b11,0b1110,0, IIC_VBIND, "vcgt", "f16", v4i16, v4f16,
5079-
NEONvcgt, 0>,
5066+
ARMvcgt, 0>,
50805067
Requires<[HasNEON, HasFullFP16]>;
50815068
def VCGThq : N3VQ<1,0,0b11,0b1110,0, IIC_VBINQ, "vcgt", "f16", v8i16, v8f16,
5082-
NEONvcgt, 0>,
5069+
ARMvcgt, 0>,
50835070
Requires<[HasNEON, HasFullFP16]>;
50845071

50855072
let TwoOperandAliasConstraint = "$Vm = $Vd" in {
50865073
defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
5087-
"$Vd, $Vm, #0", NEONvcgtz>;
5074+
"$Vd, $Vm, #0", ARMvcgtz>;
50885075
defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
5089-
"$Vd, $Vm, #0", NEONvcltz>;
5076+
"$Vd, $Vm, #0", ARMvcltz>;
50905077
}
50915078

50925079
// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)

0 commit comments

Comments
 (0)