@@ -96,10 +96,6 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
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unsigned AMDGPURegisterBankInfo::getBreakDownCost (
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const ValueMapping &ValMapping,
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const RegisterBank *CurBank) const {
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- // Currently we should only see rewrites of defs since copies from VGPR to
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- // SGPR are illegal.
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- assert (CurBank == nullptr && " shouldn't see already assigned bank" );
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-
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assert (ValMapping.NumBreakDowns == 2 &&
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ValMapping.BreakDown [0 ].Length == 32 &&
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ValMapping.BreakDown [0 ].StartIdx == 0 &&
@@ -253,10 +249,10 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
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AltMappings.push_back (&SSMapping);
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const InstructionMapping &VVMapping = getInstructionMapping (2 , 1 ,
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- getOperandsMapping ({AMDGPU::getValueMapping (AMDGPU::VGPRRegBankID, Size ),
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+ getOperandsMapping ({AMDGPU::getValueMappingSGPR64Only (AMDGPU::VGPRRegBankID, Size ),
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AMDGPU::getValueMapping (AMDGPU::VCCRegBankID, 1 ),
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- AMDGPU::getValueMapping (AMDGPU::VGPRRegBankID, Size ),
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- AMDGPU::getValueMapping (AMDGPU::VGPRRegBankID, Size )}),
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+ AMDGPU::getValueMappingSGPR64Only (AMDGPU::VGPRRegBankID, Size ),
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+ AMDGPU::getValueMappingSGPR64Only (AMDGPU::VGPRRegBankID, Size )}),
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4 ); // Num Operands
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AltMappings.push_back (&VVMapping);
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@@ -336,6 +332,43 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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unsigned Opc = MI.getOpcode ();
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MachineRegisterInfo &MRI = OpdMapper.getMRI ();
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switch (Opc) {
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+ case AMDGPU::G_SELECT: {
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+ unsigned DstReg = MI.getOperand (0 ).getReg ();
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+ LLT DstTy = MRI.getType (DstReg);
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+ if (DstTy.getSizeInBits () != 64 )
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+ break ;
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+
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+ SmallVector<unsigned , 2 > DefRegs (OpdMapper.getVRegs (0 ));
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+ SmallVector<unsigned , 1 > Src0Regs (OpdMapper.getVRegs (1 ));
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+ SmallVector<unsigned , 2 > Src1Regs (OpdMapper.getVRegs (2 ));
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+ SmallVector<unsigned , 2 > Src2Regs (OpdMapper.getVRegs (3 ));
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+
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+ // All inputs are SGPRs, nothing special to do.
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+ if (DefRegs.empty ()) {
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+ assert (Src1Regs.empty () && Src2Regs.empty ());
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+ break ;
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+ }
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+
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+ MachineIRBuilder B (MI);
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+ if (Src0Regs.empty ())
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+ Src0Regs.push_back (MI.getOperand (1 ).getReg ());
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+ else {
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+ assert (Src0Regs.size () == 1 );
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+ }
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+
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+ if (Src1Regs.empty ())
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+ split64BitValueForMapping (B, Src1Regs, MI.getOperand (2 ).getReg ());
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+
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+ if (Src2Regs.empty ())
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+ split64BitValueForMapping (B, Src2Regs, MI.getOperand (3 ).getReg ());
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+
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+ B.buildSelect (DefRegs[0 ], Src0Regs[0 ], Src1Regs[0 ], Src2Regs[0 ]);
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+ B.buildSelect (DefRegs[1 ], Src0Regs[0 ], Src1Regs[1 ], Src2Regs[1 ]);
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+
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+ MRI.setRegBank (DstReg, getRegBank (AMDGPU::VGPRRegBankID));
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+ MI.eraseFromParent ();
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+ return ;
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+ }
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case AMDGPU::G_AND:
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case AMDGPU::G_OR:
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case AMDGPU::G_XOR: {
@@ -871,10 +904,19 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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Op3Bank == AMDGPU::SGPRRegBankID;
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unsigned Bank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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Op1Bank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
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- OpdsMapping[0 ] = AMDGPU::getValueMapping (Bank, Size );
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- OpdsMapping[1 ] = AMDGPU::getValueMapping (Op1Bank, 1 );
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- OpdsMapping[2 ] = AMDGPU::getValueMapping (Bank, Size );
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- OpdsMapping[3 ] = AMDGPU::getValueMapping (Bank, Size );
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+
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+ if (Size == 64 ) {
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+ OpdsMapping[0 ] = AMDGPU::getValueMappingSGPR64Only (Bank, Size );
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+ OpdsMapping[1 ] = AMDGPU::getValueMapping (Op1Bank, 1 );
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+ OpdsMapping[2 ] = AMDGPU::getValueMappingSGPR64Only (Bank, Size );
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+ OpdsMapping[3 ] = AMDGPU::getValueMappingSGPR64Only (Bank, Size );
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+ } else {
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+ OpdsMapping[0 ] = AMDGPU::getValueMapping (Bank, Size );
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+ OpdsMapping[1 ] = AMDGPU::getValueMapping (Op1Bank, 1 );
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+ OpdsMapping[2 ] = AMDGPU::getValueMapping (Bank, Size );
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+ OpdsMapping[3 ] = AMDGPU::getValueMapping (Bank, Size );
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+ }
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+
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break ;
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}
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