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AMDGPU/GlobalISel: Handle split for 64-bit VALU select
llvm-svn: 354065
1 parent bbb8129 commit d3d4963

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3 files changed

+455
-12
lines changed

3 files changed

+455
-12
lines changed

llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,8 @@ const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
151151

152152
const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID,
153153
unsigned Size) {
154-
assert(Size == 64);
154+
if (Size != 64)
155+
return getValueMapping(BankID, Size);
155156

156157
if (BankID == AMDGPU::VGPRRegBankID)
157158
return &ValMappingsSGPR64OnlyVGPR32[4];

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 53 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -96,10 +96,6 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
9696
unsigned AMDGPURegisterBankInfo::getBreakDownCost(
9797
const ValueMapping &ValMapping,
9898
const RegisterBank *CurBank) const {
99-
// Currently we should only see rewrites of defs since copies from VGPR to
100-
// SGPR are illegal.
101-
assert(CurBank == nullptr && "shouldn't see already assigned bank");
102-
10399
assert(ValMapping.NumBreakDowns == 2 &&
104100
ValMapping.BreakDown[0].Length == 32 &&
105101
ValMapping.BreakDown[0].StartIdx == 0 &&
@@ -253,10 +249,10 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
253249
AltMappings.push_back(&SSMapping);
254250

255251
const InstructionMapping &VVMapping = getInstructionMapping(2, 1,
256-
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
252+
getOperandsMapping({AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
257253
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
258-
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
259-
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
254+
AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
255+
AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}),
260256
4); // Num Operands
261257
AltMappings.push_back(&VVMapping);
262258

@@ -336,6 +332,43 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
336332
unsigned Opc = MI.getOpcode();
337333
MachineRegisterInfo &MRI = OpdMapper.getMRI();
338334
switch (Opc) {
335+
case AMDGPU::G_SELECT: {
336+
unsigned DstReg = MI.getOperand(0).getReg();
337+
LLT DstTy = MRI.getType(DstReg);
338+
if (DstTy.getSizeInBits() != 64)
339+
break;
340+
341+
SmallVector<unsigned, 2> DefRegs(OpdMapper.getVRegs(0));
342+
SmallVector<unsigned, 1> Src0Regs(OpdMapper.getVRegs(1));
343+
SmallVector<unsigned, 2> Src1Regs(OpdMapper.getVRegs(2));
344+
SmallVector<unsigned, 2> Src2Regs(OpdMapper.getVRegs(3));
345+
346+
// All inputs are SGPRs, nothing special to do.
347+
if (DefRegs.empty()) {
348+
assert(Src1Regs.empty() && Src2Regs.empty());
349+
break;
350+
}
351+
352+
MachineIRBuilder B(MI);
353+
if (Src0Regs.empty())
354+
Src0Regs.push_back(MI.getOperand(1).getReg());
355+
else {
356+
assert(Src0Regs.size() == 1);
357+
}
358+
359+
if (Src1Regs.empty())
360+
split64BitValueForMapping(B, Src1Regs, MI.getOperand(2).getReg());
361+
362+
if (Src2Regs.empty())
363+
split64BitValueForMapping(B, Src2Regs, MI.getOperand(3).getReg());
364+
365+
B.buildSelect(DefRegs[0], Src0Regs[0], Src1Regs[0], Src2Regs[0]);
366+
B.buildSelect(DefRegs[1], Src0Regs[0], Src1Regs[1], Src2Regs[1]);
367+
368+
MRI.setRegBank(DstReg, getRegBank(AMDGPU::VGPRRegBankID));
369+
MI.eraseFromParent();
370+
return;
371+
}
339372
case AMDGPU::G_AND:
340373
case AMDGPU::G_OR:
341374
case AMDGPU::G_XOR: {
@@ -871,10 +904,19 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
871904
Op3Bank == AMDGPU::SGPRRegBankID;
872905
unsigned Bank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
873906
Op1Bank = SGPRSrcs ? AMDGPU::SCCRegBankID : AMDGPU::VCCRegBankID;
874-
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size);
875-
OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
876-
OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);
877-
OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);
907+
908+
if (Size == 64) {
909+
OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(Bank, Size);
910+
OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
911+
OpdsMapping[2] = AMDGPU::getValueMappingSGPR64Only(Bank, Size);
912+
OpdsMapping[3] = AMDGPU::getValueMappingSGPR64Only(Bank, Size);
913+
} else {
914+
OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size);
915+
OpdsMapping[1] = AMDGPU::getValueMapping(Op1Bank, 1);
916+
OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);
917+
OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);
918+
}
919+
878920
break;
879921
}
880922

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