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[msan] Handle llvm.x86.vcvtps2ph.128/256 explicitly
Check whether each lane is fully initialized, and propagate the shadow per lane instead of using the strict handling of visitInstruction. Changes the tests from llvm#129807
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-63
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2 files changed

+130
-63
lines changed

‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3273,6 +3273,60 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
32733273
setOriginForNaryOp(I);
32743274
}
32753275

3276+
/// Handle x86 SSE single-precision to half-precision conversion.
3277+
///
3278+
/// e.g.,
3279+
/// <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
3280+
/// <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)
3281+
/// Note: if the output has more elements, they are zero-initialized (and
3282+
/// therefore the shadow will also be initialized).
3283+
///
3284+
/// This differs from handleSSEVectorConvertIntrinsic() because it
3285+
/// propagates uninitialized shadow (instead of checking the shadow).
3286+
void handleSSEVectorConvertIntrinsicByProp(IntrinsicInst &I) {
3287+
assert(I.arg_size() == 2);
3288+
Value *Src = I.getArgOperand(0);
3289+
assert(Src->getType()->isVectorTy());
3290+
Value *RoundingMode = I.getArgOperand(1);
3291+
assert(RoundingMode->getType()->isIntegerTy());
3292+
3293+
// The return type might have more elements than the input.
3294+
// Temporarily shrink the return type's number of elements.
3295+
VectorType *ShadowType = cast<VectorType>(getShadowTy(&I));
3296+
if (ShadowType->getElementCount() == cast<VectorType>(Src->getType())->getElementCount() * 2)
3297+
ShadowType = VectorType::getHalfElementsVectorType(ShadowType);
3298+
3299+
assert(ShadowType->getElementCount() == cast<VectorType>(Src->getType())->getElementCount());
3300+
3301+
IRBuilder<> IRB(&I);
3302+
Value *S0 = getShadow(&I, 0);
3303+
3304+
/// For scalars:
3305+
/// Since they are converting from floating-point to integer, the output is
3306+
/// - fully uninitialized if *any* bit of the input is uninitialized
3307+
/// - fully ininitialized if all bits of the input are ininitialized
3308+
/// We apply the same principle on a per-field basis for vectors.
3309+
Value *Shadow = IRB.CreateSExt(IRB.CreateICmpNE(S0, getCleanShadow(S0)),
3310+
ShadowType);
3311+
3312+
// The return type might have more elements than the input.
3313+
// Extend the return type back to its original width.
3314+
Value *FullShadow = getCleanShadow(&I);
3315+
3316+
if (Shadow->getType() == FullShadow->getType())
3317+
FullShadow = Shadow;
3318+
else {
3319+
for (unsigned int i = 0; i < cast<FixedVectorType>(Src->getType())->getNumElements(); i++) {
3320+
Value *Elem = IRB.CreateExtractElement(Shadow, i);
3321+
FullShadow = IRB.CreateInsertElement(FullShadow, Elem, i);
3322+
}
3323+
}
3324+
3325+
setShadow(&I, FullShadow);
3326+
setOriginForNaryOp(I);
3327+
}
3328+
3329+
32763330
// Instrument x86 SSE vector convert intrinsic.
32773331
//
32783332
// This function instruments intrinsics like cvtsi2ss:
@@ -4868,6 +4922,12 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
48684922
break;
48694923
}
48704924

4925+
case Intrinsic::x86_vcvtps2ph_128:
4926+
case Intrinsic::x86_vcvtps2ph_256: {
4927+
handleSSEVectorConvertIntrinsicByProp(I);
4928+
break;
4929+
}
4930+
48714931
case Intrinsic::fshl:
48724932
case Intrinsic::fshr:
48734933
handleFunnelShift(I);

‎llvm/test/Instrumentation/MemorySanitizer/X86/f16c-intrinsics.ll

Lines changed: 70 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,18 @@ define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0) #0 {
1414
; CHECK-SAME: <4 x float> [[A0:%.*]]) #[[ATTR0:[0-9]+]] {
1515
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
1616
; CHECK-NEXT: call void @llvm.donothing()
17-
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i128
18-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0
19-
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1:![0-9]+]]
20-
; CHECK: [[BB3]]:
21-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]
22-
; CHECK-NEXT: unreachable
23-
; CHECK: [[BB4]]:
17+
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer
18+
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i16>
19+
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i16> [[TMP3]], i64 0
20+
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> zeroinitializer, i16 [[TMP4]], i64 0
21+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i16> [[TMP3]], i64 1
22+
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[TMP6]], i64 1
23+
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i16> [[TMP3]], i64 2
24+
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP7]], i16 [[TMP8]], i64 2
25+
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i16> [[TMP3]], i64 3
26+
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[TMP10]], i64 3
2427
; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[A0]], i32 0)
25-
; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8
28+
; CHECK-NEXT: store <8 x i16> [[TMP11]], ptr @__msan_retval_tls, align 8
2629
; CHECK-NEXT: ret <8 x i16> [[RES]]
2730
;
2831
%res = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
@@ -35,15 +38,10 @@ define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) #0 {
3538
; CHECK-SAME: <8 x float> [[A0:%.*]]) #[[ATTR0]] {
3639
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
3740
; CHECK-NEXT: call void @llvm.donothing()
38-
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to i256
39-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0
40-
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
41-
; CHECK: [[BB3]]:
42-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
43-
; CHECK-NEXT: unreachable
44-
; CHECK: [[BB4]]:
41+
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer
42+
; CHECK-NEXT: [[TMP3:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i16>
4543
; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> [[A0]], i32 0)
46-
; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8
44+
; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8
4745
; CHECK-NEXT: ret <8 x i16> [[RES]]
4846
;
4947
%res = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0) ; <<8 x i16>> [#uses=1]
@@ -59,24 +57,19 @@ define void @test_x86_vcvtps2ph_256_m(ptr nocapture %d, <8 x float> %a) nounwind
5957
; CHECK-NEXT: [[TMP17:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
6058
; CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr @__msan_param_tls, align 8
6159
; CHECK-NEXT: call void @llvm.donothing()
62-
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP17]] to i256
63-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 0
64-
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
65-
; CHECK: [[BB3]]:
66-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
67-
; CHECK-NEXT: unreachable
68-
; CHECK: [[BB4]]:
60+
; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <8 x i32> [[TMP17]], zeroinitializer
61+
; CHECK-NEXT: [[TMP21:%.*]] = sext <8 x i1> [[TMP20]] to <8 x i16>
6962
; CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> [[A]], i32 3)
7063
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP18]], 0
71-
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
72-
; CHECK: [[BB6]]:
73-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
64+
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1:![0-9]+]]
65+
; CHECK: [[BB5]]:
66+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]
7467
; CHECK-NEXT: unreachable
75-
; CHECK: [[BB7]]:
68+
; CHECK: [[BB6]]:
7669
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[D]] to i64
7770
; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
7871
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
79-
; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[TMP3]], align 16
72+
; CHECK-NEXT: store <8 x i16> [[TMP21]], ptr [[TMP3]], align 16
8073
; CHECK-NEXT: store <8 x i16> [[TMP0]], ptr [[D]], align 16
8174
; CHECK-NEXT: ret void
8275
;
@@ -93,25 +86,29 @@ define void @test_x86_vcvtps2ph_128_m(ptr nocapture %d, <4 x float> %a) nounwind
9386
; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
9487
; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr @__msan_param_tls, align 8
9588
; CHECK-NEXT: call void @llvm.donothing()
96-
; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP9]] to i128
97-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0
98-
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
99-
; CHECK: [[BB3]]:
100-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
101-
; CHECK-NEXT: unreachable
102-
; CHECK: [[BB4]]:
89+
; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer
90+
; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i1> [[TMP12]] to <4 x i16>
91+
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i16> [[TMP13]], i64 0
92+
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> zeroinitializer, i16 [[TMP14]], i64 0
93+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i16> [[TMP13]], i64 1
94+
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[TMP6]], i64 1
95+
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i16> [[TMP13]], i64 2
96+
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i16> [[TMP7]], i16 [[TMP8]], i64 2
97+
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i16> [[TMP13]], i64 3
98+
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i16> [[TMP15]], i16 [[TMP16]], i64 3
10399
; CHECK-NEXT: [[TMP0:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[A]], i32 3)
100+
; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP11]], <8 x i16> splat (i16 -1), <4 x i32> <i32 0, i32 1, i32 2, i32 3>
104101
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
105102
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP10]], 0
106-
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
107-
; CHECK: [[BB7]]:
103+
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]
104+
; CHECK: [[BB14]]:
108105
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
109106
; CHECK-NEXT: unreachable
110-
; CHECK: [[BB8]]:
107+
; CHECK: [[BB15]]:
111108
; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[D]] to i64
112109
; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080
113110
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr
114-
; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr [[TMP4]], align 8
111+
; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr [[TMP4]], align 8
115112
; CHECK-NEXT: store <4 x i16> [[TMP1]], ptr [[D]], align 8
116113
; CHECK-NEXT: ret void
117114
;
@@ -129,26 +126,31 @@ define void @test_x86_vcvtps2ph_128_m2(ptr nocapture %hf4x16, <4 x float> %f4X86
129126
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
130127
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
131128
; CHECK-NEXT: call void @llvm.donothing()
132-
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to i128
133-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0
134-
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
135-
; CHECK: [[BB3]]:
136-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
137-
; CHECK-NEXT: unreachable
138-
; CHECK: [[BB4]]:
129+
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer
130+
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i16>
131+
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i16> [[TMP3]], i64 0
132+
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> zeroinitializer, i16 [[TMP4]], i64 0
133+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i16> [[TMP3]], i64 1
134+
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[TMP6]], i64 1
135+
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i16> [[TMP3]], i64 2
136+
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP7]], i16 [[TMP8]], i64 2
137+
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i16> [[TMP3]], i64 3
138+
; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[TMP10]], i64 3
139139
; CHECK-NEXT: [[TMP11:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[F4X86]], i32 3)
140+
; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[TMP14]] to <2 x i64>
140141
; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i16> [[TMP11]] to <2 x double>
142+
; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP13]], i32 0
141143
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x double> [[TMP12]], i32 0
142144
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP1]], 0
143-
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
144-
; CHECK: [[BB7]]:
145+
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB15:.*]], label %[[BB16:.*]], !prof [[PROF1]]
146+
; CHECK: [[BB15]]:
145147
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
146148
; CHECK-NEXT: unreachable
147-
; CHECK: [[BB8]]:
149+
; CHECK: [[BB16]]:
148150
; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[HF4X16]] to i64
149151
; CHECK-NEXT: [[TMP16:%.*]] = xor i64 [[TMP15]], 87960930222080
150152
; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr
151-
; CHECK-NEXT: store i64 0, ptr [[TMP17]], align 8
153+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr [[TMP17]], align 8
152154
; CHECK-NEXT: store double [[VECEXT]], ptr [[HF4X16]], align 8
153155
; CHECK-NEXT: ret void
154156
;
@@ -167,27 +169,32 @@ define void @test_x86_vcvtps2ph_128_m3(ptr nocapture %hf4x16, <4 x float> %f4X86
167169
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
168170
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
169171
; CHECK-NEXT: call void @llvm.donothing()
170-
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to i128
171-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0
172-
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
173-
; CHECK: [[BB3]]:
174-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
175-
; CHECK-NEXT: unreachable
176-
; CHECK: [[BB4]]:
172+
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer
173+
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i16>
174+
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i16> [[TMP3]], i64 0
175+
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i16> zeroinitializer, i16 [[TMP4]], i64 0
176+
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i16> [[TMP3]], i64 1
177+
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[TMP5]], i16 [[TMP6]], i64 1
178+
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i16> [[TMP3]], i64 2
179+
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x i16> [[TMP7]], i16 [[TMP8]], i64 2
180+
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i16> [[TMP3]], i64 3
181+
; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i16> [[TMP9]], i16 [[TMP10]], i64 3
177182
; CHECK-NEXT: [[TMP11:%.*]] = tail call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> [[F4X86]], i32 3)
178-
; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i16> [[TMP11]] to <2 x i64>
183+
; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i16> [[TMP13]] to <2 x i64>
184+
; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i16> [[TMP11]] to <2 x i64>
179185
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x i64> [[TMP12]], i32 0
186+
; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <2 x i64> [[TMP14]], i32 0
180187
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP1]], 0
181-
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
182-
; CHECK: [[BB7]]:
188+
; CHECK-NEXT: br i1 [[_MSCMP1]], label %[[BB15:.*]], label %[[BB16:.*]], !prof [[PROF1]]
189+
; CHECK: [[BB15]]:
183190
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
184191
; CHECK-NEXT: unreachable
185-
; CHECK: [[BB8]]:
192+
; CHECK: [[BB16]]:
186193
; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[HF4X16]] to i64
187194
; CHECK-NEXT: [[TMP16:%.*]] = xor i64 [[TMP15]], 87960930222080
188195
; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr
189-
; CHECK-NEXT: store i64 0, ptr [[TMP17]], align 8
190-
; CHECK-NEXT: store i64 [[VECEXT]], ptr [[HF4X16]], align 8
196+
; CHECK-NEXT: store i64 [[VECEXT]], ptr [[TMP17]], align 8
197+
; CHECK-NEXT: store i64 [[VECEXT1]], ptr [[HF4X16]], align 8
191198
; CHECK-NEXT: ret void
192199
;
193200
entry:

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