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Commit 5223379

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aykevldeadprogram
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mimxrt1062: simplify arm.AsmFull to arm.Asm
This means fewer instances of arm.AsmFull, which I'd like to remove eventually if possible.
1 parent 9160f3f commit 5223379

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+21
-47
lines changed

1 file changed

+21
-47
lines changed

src/device/nxp/mimxrt1062_mpu.go

Lines changed: 21 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -142,18 +142,14 @@ func (mpu *MPU_Type) Enable(enable bool) {
142142
if enable {
143143
mpu.CTRL.Set(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk)
144144
SystemControl.SHCSR.SetBits(SCB_SHCSR_MEMFAULTENA_Msk)
145-
arm.AsmFull(`
146-
dsb 0xF
147-
isb 0xF
148-
`, nil)
145+
arm.Asm("dsb 0xF")
146+
arm.Asm("isb 0xF")
149147
enableDcache(true)
150148
enableIcache(true)
151149
} else {
152150
enableIcache(false)
153151
enableDcache(false)
154-
arm.AsmFull(`
155-
dmb 0xF
156-
`, nil)
152+
arm.Asm("dmb 0xF")
157153
SystemControl.SHCSR.ClearBits(SCB_SHCSR_MEMFAULTENA_Msk)
158154
mpu.CTRL.ClearBits(MPU_CTRL_ENABLE_Msk)
159155
}
@@ -188,31 +184,21 @@ func (mpu *MPU_Type) SetRASR(size RegionSize, access AccessPerms, ext Extension,
188184
func enableIcache(enable bool) {
189185
if enable != SystemControl.CCR.HasBits(SCB_CCR_IC_Msk) {
190186
if enable {
191-
arm.AsmFull(`
192-
dsb 0xF
193-
isb 0xF
194-
`, nil)
187+
arm.Asm("dsb 0xF")
188+
arm.Asm("isb 0xF")
195189
SystemControl.ICIALLU.Set(0)
196-
arm.AsmFull(`
197-
dsb 0xF
198-
isb 0xF
199-
`, nil)
190+
arm.Asm("dsb 0xF")
191+
arm.Asm("isb 0xF")
200192
SystemControl.CCR.SetBits(SCB_CCR_IC_Msk)
201-
arm.AsmFull(`
202-
dsb 0xF
203-
isb 0xF
204-
`, nil)
193+
arm.Asm("dsb 0xF")
194+
arm.Asm("isb 0xF")
205195
} else {
206-
arm.AsmFull(`
207-
dsb 0xF
208-
isb 0xF
209-
`, nil)
196+
arm.Asm("dsb 0xF")
197+
arm.Asm("isb 0xF")
210198
SystemControl.CCR.ClearBits(SCB_CCR_IC_Msk)
211199
SystemControl.ICIALLU.Set(0)
212-
arm.AsmFull(`
213-
dsb 0xF
214-
isb 0xF
215-
`, nil)
200+
arm.Asm("dsb 0xF")
201+
arm.Asm("isb 0xF")
216202
}
217203
}
218204
}
@@ -227,9 +213,7 @@ func enableDcache(enable bool) {
227213
if enable != SystemControl.CCR.HasBits(SCB_CCR_DC_Msk) {
228214
if enable {
229215
SystemControl.CSSELR.Set(0)
230-
arm.AsmFull(`
231-
dsb 0xF
232-
`, nil)
216+
arm.Asm("dsb 0xF")
233217
ccsidr := SystemControl.CCSIDR.Get()
234218
sets := (ccsidr & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos
235219
for sets != 0 {
@@ -242,23 +226,15 @@ func enableDcache(enable bool) {
242226
}
243227
sets--
244228
}
245-
arm.AsmFull(`
246-
dsb 0xF
247-
`, nil)
229+
arm.Asm("dsb 0xF")
248230
SystemControl.CCR.SetBits(SCB_CCR_DC_Msk)
249-
arm.AsmFull(`
250-
dsb 0xF
251-
isb 0xF
252-
`, nil)
231+
arm.Asm("dsb 0xF")
232+
arm.Asm("isb 0xF")
253233
} else {
254234
SystemControl.CSSELR.Set(0)
255-
arm.AsmFull(`
256-
dsb 0xF
257-
`, nil)
235+
arm.Asm("dsb 0xF")
258236
SystemControl.CCR.ClearBits(SCB_CCR_DC_Msk)
259-
arm.AsmFull(`
260-
dsb 0xF
261-
`, nil)
237+
arm.Asm("dsb 0xF")
262238
dcacheCcsidr.Set(SystemControl.CCSIDR.Get())
263239
dcacheSets.Set((dcacheCcsidr.Get() & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
264240
for dcacheSets.Get() != 0 {
@@ -271,10 +247,8 @@ func enableDcache(enable bool) {
271247
}
272248
dcacheSets.Set(dcacheSets.Get() - 1)
273249
}
274-
arm.AsmFull(`
275-
dsb 0xF
276-
isb 0xF
277-
`, nil)
250+
arm.Asm("dsb 0xF")
251+
arm.Asm("isb 0xF")
278252
}
279253
}
280254
}

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