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topperctopperc
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fixup! Add load/store to other locations that reference RISCV::LH/SH
1 parent 3f61dbb commit 1d4f4b6

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2 files changed

+224
-64
lines changed

2 files changed

+224
-64
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,7 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
104104
MemBytes = 1;
105105
break;
106106
case RISCV::LH:
107+
case RISCV::LH_INX:
107108
case RISCV::LHU:
108109
case RISCV::FLH:
109110
MemBytes = 2;
@@ -144,6 +145,7 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
144145
MemBytes = 1;
145146
break;
146147
case RISCV::SH:
148+
case RISCV::SH_INX:
147149
case RISCV::FSH:
148150
MemBytes = 2;
149151
break;
@@ -2576,6 +2578,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
25762578
case RISCV::LB:
25772579
case RISCV::LBU:
25782580
case RISCV::LH:
2581+
case RISCV::LH_INX:
25792582
case RISCV::LHU:
25802583
case RISCV::LW:
25812584
case RISCV::LWU:
@@ -2585,6 +2588,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
25852588
case RISCV::FLD:
25862589
case RISCV::SB:
25872590
case RISCV::SH:
2591+
case RISCV::SH_INX:
25882592
case RISCV::SW:
25892593
case RISCV::SD:
25902594
case RISCV::FSH:
@@ -2648,9 +2652,11 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
26482652
case RISCV::LBU:
26492653
case RISCV::SB:
26502654
case RISCV::LH:
2655+
case RISCV::LH_INX:
26512656
case RISCV::LHU:
26522657
case RISCV::FLH:
26532658
case RISCV::SH:
2659+
case RISCV::SH_INX:
26542660
case RISCV::FSH:
26552661
case RISCV::LW:
26562662
case RISCV::LWU:

‎llvm/test/CodeGen/RISCV/codemodel-lowering.ll

Lines changed: 218 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,24 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -code-model=small -verify-machineinstrs < %s \
3-
; RUN: | FileCheck %s -check-prefix=RV32I-SMALL
4-
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -code-model=medium -verify-machineinstrs < %s \
5-
; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM
6-
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -code-model=small -verify-machineinstrs < %s \
7-
; RUN: | FileCheck %s -check-prefix=RV64I-SMALL
8-
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -code-model=medium -verify-machineinstrs < %s \
9-
; RUN: | FileCheck %s -check-prefix=RV64I-MEDIUM
10-
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -code-model=large -verify-machineinstrs < %s \
11-
; RUN: | FileCheck %s -check-prefix=RV64I-LARGE
2+
; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=small -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32F-SMALL
4+
; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=medium -verify-machineinstrs < %s \
5+
; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32F-MEDIUM
6+
; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=small -verify-machineinstrs < %s \
7+
; RUN: | FileCheck %s -check-prefixes=RV64I-SMALL,RV64F-SMALL
8+
; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=medium -verify-machineinstrs < %s \
9+
; RUN: | FileCheck %s -check-prefixes=RV64I-MEDIUM,RV64F-MEDIUM
10+
; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh -target-abi=lp64f -code-model=large -verify-machineinstrs < %s \
11+
; RUN: | FileCheck %s -check-prefixes=RV64I-LARGE,RV64F-LARGE
12+
; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs < %s \
13+
; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32FINX-SMALL
14+
; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=medium -verify-machineinstrs < %s \
15+
; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32FINX-MEDIUM
16+
; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=small -verify-machineinstrs < %s \
17+
; RUN: | FileCheck %s -check-prefixes=RV64I-SMALL,RV64FINX-SMALL
18+
; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=medium -verify-machineinstrs < %s \
19+
; RUN: | FileCheck %s -check-prefixes=RV64I-MEDIUM,RV64FINX-MEDIUM
20+
; RUN: llc -mtriple=riscv64 -mattr=+zfinx,+zhinx -target-abi=lp64 -code-model=large -verify-machineinstrs < %s \
21+
; RUN: | FileCheck %s -check-prefixes=RV64I-LARGE,RV64FINX-LARGE
1222

1323
; Check lowering of globals
1424
@G = global i32 0
@@ -238,43 +248,78 @@ indirectgoto:
238248
; Check lowering of constantpools
239249

240250
define float @lower_constantpool(float %a) nounwind {
241-
; RV32I-SMALL-LABEL: lower_constantpool:
242-
; RV32I-SMALL: # %bb.0:
243-
; RV32I-SMALL-NEXT: lui a0, %hi(.LCPI3_0)
244-
; RV32I-SMALL-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
245-
; RV32I-SMALL-NEXT: fadd.s fa0, fa0, fa5
246-
; RV32I-SMALL-NEXT: ret
251+
; RV32F-SMALL-LABEL: lower_constantpool:
252+
; RV32F-SMALL: # %bb.0:
253+
; RV32F-SMALL-NEXT: lui a0, %hi(.LCPI3_0)
254+
; RV32F-SMALL-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
255+
; RV32F-SMALL-NEXT: fadd.s fa0, fa0, fa5
256+
; RV32F-SMALL-NEXT: ret
247257
;
248-
; RV32I-MEDIUM-LABEL: lower_constantpool:
249-
; RV32I-MEDIUM: # %bb.0:
250-
; RV32I-MEDIUM-NEXT: .Lpcrel_hi3:
251-
; RV32I-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
252-
; RV32I-MEDIUM-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0)
253-
; RV32I-MEDIUM-NEXT: fadd.s fa0, fa0, fa5
254-
; RV32I-MEDIUM-NEXT: ret
258+
; RV32F-MEDIUM-LABEL: lower_constantpool:
259+
; RV32F-MEDIUM: # %bb.0:
260+
; RV32F-MEDIUM-NEXT: .Lpcrel_hi3:
261+
; RV32F-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
262+
; RV32F-MEDIUM-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0)
263+
; RV32F-MEDIUM-NEXT: fadd.s fa0, fa0, fa5
264+
; RV32F-MEDIUM-NEXT: ret
255265
;
256-
; RV64I-SMALL-LABEL: lower_constantpool:
257-
; RV64I-SMALL: # %bb.0:
258-
; RV64I-SMALL-NEXT: lui a0, %hi(.LCPI3_0)
259-
; RV64I-SMALL-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
260-
; RV64I-SMALL-NEXT: fadd.s fa0, fa0, fa5
261-
; RV64I-SMALL-NEXT: ret
266+
; RV64F-SMALL-LABEL: lower_constantpool:
267+
; RV64F-SMALL: # %bb.0:
268+
; RV64F-SMALL-NEXT: lui a0, %hi(.LCPI3_0)
269+
; RV64F-SMALL-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
270+
; RV64F-SMALL-NEXT: fadd.s fa0, fa0, fa5
271+
; RV64F-SMALL-NEXT: ret
262272
;
263-
; RV64I-MEDIUM-LABEL: lower_constantpool:
264-
; RV64I-MEDIUM: # %bb.0:
265-
; RV64I-MEDIUM-NEXT: .Lpcrel_hi3:
266-
; RV64I-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
267-
; RV64I-MEDIUM-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0)
268-
; RV64I-MEDIUM-NEXT: fadd.s fa0, fa0, fa5
269-
; RV64I-MEDIUM-NEXT: ret
273+
; RV64F-MEDIUM-LABEL: lower_constantpool:
274+
; RV64F-MEDIUM: # %bb.0:
275+
; RV64F-MEDIUM-NEXT: .Lpcrel_hi3:
276+
; RV64F-MEDIUM-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
277+
; RV64F-MEDIUM-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0)
278+
; RV64F-MEDIUM-NEXT: fadd.s fa0, fa0, fa5
279+
; RV64F-MEDIUM-NEXT: ret
270280
;
271-
; RV64I-LARGE-LABEL: lower_constantpool:
272-
; RV64I-LARGE: # %bb.0:
273-
; RV64I-LARGE-NEXT: .Lpcrel_hi3:
274-
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
275-
; RV64I-LARGE-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0)
276-
; RV64I-LARGE-NEXT: fadd.s fa0, fa0, fa5
277-
; RV64I-LARGE-NEXT: ret
281+
; RV64F-LARGE-LABEL: lower_constantpool:
282+
; RV64F-LARGE: # %bb.0:
283+
; RV64F-LARGE-NEXT: .Lpcrel_hi3:
284+
; RV64F-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI3_0)
285+
; RV64F-LARGE-NEXT: flw fa5, %pcrel_lo(.Lpcrel_hi3)(a0)
286+
; RV64F-LARGE-NEXT: fadd.s fa0, fa0, fa5
287+
; RV64F-LARGE-NEXT: ret
288+
;
289+
; RV32FINX-SMALL-LABEL: lower_constantpool:
290+
; RV32FINX-SMALL: # %bb.0:
291+
; RV32FINX-SMALL-NEXT: lui a1, 260097
292+
; RV32FINX-SMALL-NEXT: addi a1, a1, -2048
293+
; RV32FINX-SMALL-NEXT: fadd.s a0, a0, a1
294+
; RV32FINX-SMALL-NEXT: ret
295+
;
296+
; RV32FINX-MEDIUM-LABEL: lower_constantpool:
297+
; RV32FINX-MEDIUM: # %bb.0:
298+
; RV32FINX-MEDIUM-NEXT: lui a1, 260097
299+
; RV32FINX-MEDIUM-NEXT: addi a1, a1, -2048
300+
; RV32FINX-MEDIUM-NEXT: fadd.s a0, a0, a1
301+
; RV32FINX-MEDIUM-NEXT: ret
302+
;
303+
; RV64FINX-SMALL-LABEL: lower_constantpool:
304+
; RV64FINX-SMALL: # %bb.0:
305+
; RV64FINX-SMALL-NEXT: lui a1, 260097
306+
; RV64FINX-SMALL-NEXT: addiw a1, a1, -2048
307+
; RV64FINX-SMALL-NEXT: fadd.s a0, a0, a1
308+
; RV64FINX-SMALL-NEXT: ret
309+
;
310+
; RV64FINX-MEDIUM-LABEL: lower_constantpool:
311+
; RV64FINX-MEDIUM: # %bb.0:
312+
; RV64FINX-MEDIUM-NEXT: lui a1, 260097
313+
; RV64FINX-MEDIUM-NEXT: addiw a1, a1, -2048
314+
; RV64FINX-MEDIUM-NEXT: fadd.s a0, a0, a1
315+
; RV64FINX-MEDIUM-NEXT: ret
316+
;
317+
; RV64FINX-LARGE-LABEL: lower_constantpool:
318+
; RV64FINX-LARGE: # %bb.0:
319+
; RV64FINX-LARGE-NEXT: lui a1, 260097
320+
; RV64FINX-LARGE-NEXT: addiw a1, a1, -2048
321+
; RV64FINX-LARGE-NEXT: fadd.s a0, a0, a1
322+
; RV64FINX-LARGE-NEXT: ret
278323
%1 = fadd float %a, 1.000244140625
279324
ret float %1
280325
}
@@ -289,35 +334,144 @@ define i32 @lower_extern_weak(i32 %a) nounwind {
289334
; RV32I-SMALL-NEXT: lw a0, %lo(W)(a0)
290335
; RV32I-SMALL-NEXT: ret
291336
;
292-
; RV32I-MEDIUM-LABEL: lower_extern_weak:
293-
; RV32I-MEDIUM: # %bb.0:
294-
; RV32I-MEDIUM-NEXT: .Lpcrel_hi4:
295-
; RV32I-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)
296-
; RV32I-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi4)(a0)
297-
; RV32I-MEDIUM-NEXT: lw a0, 0(a0)
298-
; RV32I-MEDIUM-NEXT: ret
337+
; RV32F-MEDIUM-LABEL: lower_extern_weak:
338+
; RV32F-MEDIUM: # %bb.0:
339+
; RV32F-MEDIUM-NEXT: .Lpcrel_hi4:
340+
; RV32F-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)
341+
; RV32F-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi4)(a0)
342+
; RV32F-MEDIUM-NEXT: lw a0, 0(a0)
343+
; RV32F-MEDIUM-NEXT: ret
299344
;
300345
; RV64I-SMALL-LABEL: lower_extern_weak:
301346
; RV64I-SMALL: # %bb.0:
302347
; RV64I-SMALL-NEXT: lui a0, %hi(W)
303348
; RV64I-SMALL-NEXT: lw a0, %lo(W)(a0)
304349
; RV64I-SMALL-NEXT: ret
305350
;
306-
; RV64I-MEDIUM-LABEL: lower_extern_weak:
307-
; RV64I-MEDIUM: # %bb.0:
308-
; RV64I-MEDIUM-NEXT: .Lpcrel_hi4:
309-
; RV64I-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)
310-
; RV64I-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0)
311-
; RV64I-MEDIUM-NEXT: lw a0, 0(a0)
312-
; RV64I-MEDIUM-NEXT: ret
351+
; RV64F-MEDIUM-LABEL: lower_extern_weak:
352+
; RV64F-MEDIUM: # %bb.0:
353+
; RV64F-MEDIUM-NEXT: .Lpcrel_hi4:
354+
; RV64F-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)
355+
; RV64F-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0)
356+
; RV64F-MEDIUM-NEXT: lw a0, 0(a0)
357+
; RV64F-MEDIUM-NEXT: ret
313358
;
314-
; RV64I-LARGE-LABEL: lower_extern_weak:
315-
; RV64I-LARGE: # %bb.0:
316-
; RV64I-LARGE-NEXT: .Lpcrel_hi4:
317-
; RV64I-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI4_0)
318-
; RV64I-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0)
319-
; RV64I-LARGE-NEXT: lw a0, 0(a0)
320-
; RV64I-LARGE-NEXT: ret
359+
; RV64F-LARGE-LABEL: lower_extern_weak:
360+
; RV64F-LARGE: # %bb.0:
361+
; RV64F-LARGE-NEXT: .Lpcrel_hi4:
362+
; RV64F-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI4_0)
363+
; RV64F-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi4)(a0)
364+
; RV64F-LARGE-NEXT: lw a0, 0(a0)
365+
; RV64F-LARGE-NEXT: ret
366+
;
367+
; RV32FINX-MEDIUM-LABEL: lower_extern_weak:
368+
; RV32FINX-MEDIUM: # %bb.0:
369+
; RV32FINX-MEDIUM-NEXT: .Lpcrel_hi3:
370+
; RV32FINX-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)
371+
; RV32FINX-MEDIUM-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi3)(a0)
372+
; RV32FINX-MEDIUM-NEXT: lw a0, 0(a0)
373+
; RV32FINX-MEDIUM-NEXT: ret
374+
;
375+
; RV64FINX-MEDIUM-LABEL: lower_extern_weak:
376+
; RV64FINX-MEDIUM: # %bb.0:
377+
; RV64FINX-MEDIUM-NEXT: .Lpcrel_hi3:
378+
; RV64FINX-MEDIUM-NEXT: auipc a0, %got_pcrel_hi(W)
379+
; RV64FINX-MEDIUM-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0)
380+
; RV64FINX-MEDIUM-NEXT: lw a0, 0(a0)
381+
; RV64FINX-MEDIUM-NEXT: ret
382+
;
383+
; RV64FINX-LARGE-LABEL: lower_extern_weak:
384+
; RV64FINX-LARGE: # %bb.0:
385+
; RV64FINX-LARGE-NEXT: .Lpcrel_hi3:
386+
; RV64FINX-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI4_0)
387+
; RV64FINX-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi3)(a0)
388+
; RV64FINX-LARGE-NEXT: lw a0, 0(a0)
389+
; RV64FINX-LARGE-NEXT: ret
321390
%1 = load volatile i32, ptr @W
322391
ret i32 %1
323392
}
393+
394+
@X = global half 1.5
395+
396+
define half @lower_global_half(half %a) nounwind {
397+
; RV32F-SMALL-LABEL: lower_global_half:
398+
; RV32F-SMALL: # %bb.0:
399+
; RV32F-SMALL-NEXT: lui a0, %hi(X)
400+
; RV32F-SMALL-NEXT: flh fa5, %lo(X)(a0)
401+
; RV32F-SMALL-NEXT: fadd.h fa0, fa0, fa5
402+
; RV32F-SMALL-NEXT: ret
403+
;
404+
; RV32F-MEDIUM-LABEL: lower_global_half:
405+
; RV32F-MEDIUM: # %bb.0:
406+
; RV32F-MEDIUM-NEXT: .Lpcrel_hi5:
407+
; RV32F-MEDIUM-NEXT: auipc a0, %pcrel_hi(X)
408+
; RV32F-MEDIUM-NEXT: flh fa5, %pcrel_lo(.Lpcrel_hi5)(a0)
409+
; RV32F-MEDIUM-NEXT: fadd.h fa0, fa0, fa5
410+
; RV32F-MEDIUM-NEXT: ret
411+
;
412+
; RV64F-SMALL-LABEL: lower_global_half:
413+
; RV64F-SMALL: # %bb.0:
414+
; RV64F-SMALL-NEXT: lui a0, %hi(X)
415+
; RV64F-SMALL-NEXT: flh fa5, %lo(X)(a0)
416+
; RV64F-SMALL-NEXT: fadd.h fa0, fa0, fa5
417+
; RV64F-SMALL-NEXT: ret
418+
;
419+
; RV64F-MEDIUM-LABEL: lower_global_half:
420+
; RV64F-MEDIUM: # %bb.0:
421+
; RV64F-MEDIUM-NEXT: .Lpcrel_hi5:
422+
; RV64F-MEDIUM-NEXT: auipc a0, %pcrel_hi(X)
423+
; RV64F-MEDIUM-NEXT: flh fa5, %pcrel_lo(.Lpcrel_hi5)(a0)
424+
; RV64F-MEDIUM-NEXT: fadd.h fa0, fa0, fa5
425+
; RV64F-MEDIUM-NEXT: ret
426+
;
427+
; RV64F-LARGE-LABEL: lower_global_half:
428+
; RV64F-LARGE: # %bb.0:
429+
; RV64F-LARGE-NEXT: .Lpcrel_hi5:
430+
; RV64F-LARGE-NEXT: auipc a0, %pcrel_hi(.LCPI5_0)
431+
; RV64F-LARGE-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi5)(a0)
432+
; RV64F-LARGE-NEXT: flh fa5, 0(a0)
433+
; RV64F-LARGE-NEXT: fadd.h fa0, fa0, fa5
434+
; RV64F-LARGE-NEXT: ret
435+
;
436+
; RV32FINX-SMALL-LABEL: lower_global_half:
437+
; RV32FINX-SMALL: # %bb.0:
438+
; RV32FINX-SMALL-NEXT: lui a1, %hi(X)
439+
; RV32FINX-SMALL-NEXT: lh a1, %lo(X)(a1)
440+
; RV32FINX-SMALL-NEXT: fadd.h a0, a0, a1
441+
; RV32FINX-SMALL-NEXT: ret
442+
;
443+
; RV32FINX-MEDIUM-LABEL: lower_global_half:
444+
; RV32FINX-MEDIUM: # %bb.0:
445+
; RV32FINX-MEDIUM-NEXT: .Lpcrel_hi4:
446+
; RV32FINX-MEDIUM-NEXT: auipc a1, %pcrel_hi(X)
447+
; RV32FINX-MEDIUM-NEXT: lh a1, %pcrel_lo(.Lpcrel_hi4)(a1)
448+
; RV32FINX-MEDIUM-NEXT: fadd.h a0, a0, a1
449+
; RV32FINX-MEDIUM-NEXT: ret
450+
;
451+
; RV64FINX-SMALL-LABEL: lower_global_half:
452+
; RV64FINX-SMALL: # %bb.0:
453+
; RV64FINX-SMALL-NEXT: lui a1, %hi(X)
454+
; RV64FINX-SMALL-NEXT: lh a1, %lo(X)(a1)
455+
; RV64FINX-SMALL-NEXT: fadd.h a0, a0, a1
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; RV64FINX-SMALL-NEXT: ret
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;
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; RV64FINX-MEDIUM-LABEL: lower_global_half:
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; RV64FINX-MEDIUM: # %bb.0:
460+
; RV64FINX-MEDIUM-NEXT: .Lpcrel_hi4:
461+
; RV64FINX-MEDIUM-NEXT: auipc a1, %pcrel_hi(X)
462+
; RV64FINX-MEDIUM-NEXT: lh a1, %pcrel_lo(.Lpcrel_hi4)(a1)
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; RV64FINX-MEDIUM-NEXT: fadd.h a0, a0, a1
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; RV64FINX-MEDIUM-NEXT: ret
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;
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; RV64FINX-LARGE-LABEL: lower_global_half:
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; RV64FINX-LARGE: # %bb.0:
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; RV64FINX-LARGE-NEXT: .Lpcrel_hi4:
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; RV64FINX-LARGE-NEXT: auipc a1, %pcrel_hi(.LCPI5_0)
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; RV64FINX-LARGE-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi4)(a1)
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; RV64FINX-LARGE-NEXT: lh a1, 0(a1)
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; RV64FINX-LARGE-NEXT: fadd.h a0, a0, a1
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; RV64FINX-LARGE-NEXT: ret
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%b = load half, ptr @X
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%1 = fadd half %a, %b
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ret half %1
477+
}

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