Fixed various typos in prompts

dataset_spec-to-rtl/Prob027_fadd_prompt.txt

@@ -9,6 +9,6 @@ specified.
  - output cout
  - output sum
 
-The module should impement a full adder. A full adder adds three bits
+The module should implement a full adder. A full adder adds three bits
 (including carry-in) and produces a sum and carry-out.
 

dataset_spec-to-rtl/Prob028_m2014_q4a_prompt.txt

@@ -7,5 +7,5 @@ specified.
  - input  ena
  - output q
 
-The module should impement a D latch using an always block.
+The module should implement a D latch using an always block.
 

dataset_spec-to-rtl/Prob029_m2014_q4g_prompt.txt

@@ -8,7 +8,7 @@ specified.
  - input  in3
  - output out
 
-The module should impement the following circuit: A two-input XNOR
+The module should implement the following circuit: A two-input XNOR
 (connected to 'in1' and 'in2) has an output connected to the input of a
 two-input XOR. The second input of the XOR is 'in3.' The output of the
 XOR is 'out'.

dataset_spec-to-rtl/Prob061_2014_q4a_prompt.txt

@@ -12,7 +12,7 @@ specified.
 
 The module will be one stage in a larger n-bit shift register circuit.
 Input E is for enabling shift, R for value to load, L is asserted when it
-should load, and w is the input from the prevous stage of the shift
+should load, and w is the input from the previous stage of the shift
 register. Assume all sequential logic is triggered on the positive edge
 of the clock.
 

dataset_spec-to-rtl/Prob099_m2014_q6c_prompt.txt

@@ -27,9 +27,9 @@ Resets into state A. For this part, assume that a one-hot code is used
 with the state assignment y[5:0] = 000001, 000010, 000100, 001000,
 010000, 100000 for states A, B,..., F, respectively.
 
-The module shou module ment the next-state signals Y2 and Y4
+The module should implement the next-state signals Y2 and Y4
 corresponding to signal y[1] and y[3]. Derive the logic equations by
 inspection assuming the one-hot encoding.
  implement the next-state signals  and corresponding to
-signal y[1] and y[3]Derive the logic equations byinspection assuming the one-hot encoding.
+signal y[1] and y[3]Derive the logic equations by inspection assuming the one-hot encoding.
 

dataset_spec-to-rtl/Prob142_lemmings2_prompt.txt

@@ -31,7 +31,7 @@ disappears (but not yet falling), or when the ground reappears while
 still falling, also does not affect the walking direction.
 
 Implement a Moore state machine that models this behaviour. areset is
-positive edge triggered asynchronous reseting the Lemming machine to walk
+positive edge triggered asynchronous resetting the Lemming machine to walk
 left. Assume all sequential logic is triggered on the positive edge of
 the clock.
 

dataset_spec-to-rtl/Prob144_conwaylife_prompt.txt

@@ -8,7 +8,7 @@ specified.
  - input  data (256 bits)
  - output q (256 bits)
 
-The module should implemement a "game" played on a two-dimensional grid
+The module should impalement a "game" played on a two-dimensional grid
 of cells, where each cell is either 1 (alive) or 0 (dead). At each time
 step, each cell changes state depending on how many neighbours it has:
 

dataset_spec-to-rtl/Prob149_ece241_2013_q4_prompt.txt

@@ -11,8 +11,8 @@ specified.
  - output fr0
  - output dfr
 
-A large reservior of water serves several users. In order to keep the
-level of water succificently high, three sensors are placed vertically at
+A large reservoir of water serves several users. In order to keep the
+level of water sufficiently high, three sensors are placed vertically at
 5-inch intervals. When the water level is above the highest sensor s[2],
 the input flow rate should be zero. When the level is below the lowest
 sensor s[0], the flow rate should be at maximum (both Nominal flow valve

dataset_spec-to-rtl/Prob151_review2015_fsm_prompt.txt

@@ -27,7 +27,7 @@ The serial data is available on the data input pin. When the pattern 1101
 is received, the state machine must then assert output shift_ena for
 exactly 4 clock cycles. After that, the state machine asserts its
 counting output to indicate it is waiting for the counters, and waits
-until input done_counting is high.At that point, the state machine must
+until input done_counting is high. At that point, the state machine must
 assert done to notify the user the timer has timed out, and waits until
 input ack is 1 before being reset to look for the next occurrence of the
 start sequence (1101). The state machine should have a active high

dataset_spec-to-rtl/Prob152_lemmings3_prompt.txt

@@ -45,7 +45,7 @@ these conditions are satisfied, fall has higher precedence than dig,
 which has higher precedence than switching directions.)
 
 Implement a Moore state machine that models this behaviour. areset is
-positive edge triggered asynchronous reseting the Lemming machine to walk
+positive edge triggered asynchronous resetting the Lemming machine to walk
 left. Assume all sequential logic is triggered on the positive edge of
 the clock.
 

dataset_spec-to-rtl/Prob155_lemmings4_prompt.txt

@@ -54,7 +54,7 @@ Lemmings only splatter when hitting the ground; they do not splatter in
 mid-air.
 
 Implement a Moore state machine that models this behaviour. areset is
-positive edge triggered asynchronous reseting the Lemming machine to walk
+positive edge triggered asynchronous resetting the Lemming machine to walk
 left.
 
 Assume all sequential logic is triggered on the positive edge of the