Skip to content

[libcpu][risc-v] fix the bug when using ASID in the RV64 MMU. #9511

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Oct 11, 2024

Conversation

zhangjing0303
Copy link
Contributor

Corrected the SATP register to ensure it uses the correct 64-bit format as required by the system architecture.

拉取/合并请求描述:(PR description)

[

为什么提交这份PR (why to submit this PR)

For the qemu-virt64-riscv BSP, when running the smart version, the system fails to boot properly if ARCH_USING_ASID=y.

你的解决方案是什么 (what is your solution)

Change the type of the variable satp_reg in rt_hw_asid_init to rt_uint64_t.

请提供验证的bsp和config (provide the config and bsp)

  • BSP: bsp/qemu-virt64-riscv
  • .config: CONFIG_ARCH_USING_ASID=y
  • action:

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

  • 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
  • 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality:

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

  • 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
  • 代码风格正确,包括缩进空格,命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
  • 没有垃圾代码,代码尽量精简,不包含#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up
  • 所有变更均有原因及合理的,并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
  • 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
  • 代码是高质量的 Code in this PR is of high quality
  • 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification

Corrected the SATP register to ensure it uses the correct 64-bit format as required by the system architecture.
@CLAassistant
Copy link

CLAassistant commented Oct 8, 2024

CLA assistant check
All committers have signed the CLA.

@github-actions github-actions bot added Arch: RISC-V BSP related with risc-v libcpu labels Oct 8, 2024
@mysterywolf mysterywolf requested review from Rbb666 and polarvid October 8, 2024 21:58
@mysterywolf mysterywolf added the wait_+2 wait for "+2" to confirm label Oct 10, 2024
@mysterywolf mysterywolf merged commit 523b123 into RT-Thread:master Oct 11, 2024
43 of 44 checks passed
@zhangjing0303 zhangjing0303 deleted the rv64-fix-mmu-asid branch October 11, 2024 07:19
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Arch: RISC-V BSP related with risc-v libcpu +1 Agree +1 +2 Agree +2
Projects
None yet
Development

Successfully merging this pull request may close these issues.

5 participants