$ cat mem.rtlil
attribute \generator "Amaranth"
attribute \top 1
module \top
  attribute \src "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227"
  wire width 8 input 0 \addr
  attribute \src "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/lib/wiring.py:227"
  wire width 29 output 1 \fields
  attribute \src "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/ir.py:508"
  wire width 1 input 2 \clk
  attribute \src "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/.venv/lib/python3.11/site-packages/amaranth/hdl/ir.py:508"
  wire width 1 input 3 \rst
  attribute \src "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/src/sentinel/ucoderom.py:42"
  wire width 1 \ucode_mem_r_en
  attribute \src "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/src/sentinel/ucoderom.py:42"
  wire width 8 \ucode_mem_r_addr
  attribute \src "C:/msys64/home/William/Projects/FPGA/amaranth/sentinel/src/sentinel/ucoderom.py:42"
  wire width 32 \ucode_mem_r_data
  cell $mem_v2 \rdport
    parameter \SIZE 256
    parameter \OFFSET 0
    parameter \ABITS 8
    parameter \WIDTH 32
    parameter \INIT 8192'10110000000000010101000000000000000000000000000000000000010100000000110000
    parameter \RD_PORTS 1
    parameter \RD_CLK_ENABLE 1'1
    parameter \RD_CLK_POLARITY 1'1
    parameter \RD_TRANSPARENCY_MASK 1'0
    parameter \RD_COLLISION_X_MASK 1'0
    parameter \RD_WIDE_CONTINUATION 1'0
    parameter \RD_CE_OVER_SRST 1'0
    parameter \RD_ARST_VALUE 32'00000000000000000000000000000000
    parameter \RD_SRST_VALUE 32'00000000000000000000000000000000
    parameter \RD_INIT_VALUE 32'00000000000000000000000000000000
    parameter \WR_PORTS 0
    parameter \WR_CLK_ENABLE 1'0
    parameter \WR_CLK_POLARITY 1'0
    parameter \WR_PRIORITY_MASK 1'0
    parameter \WR_WIDE_CONTINUATION 1'0
    parameter \MEMID "\\rdport"
    connect \RD_CLK { \clk }
    connect \RD_EN { \ucode_mem_r_en }
    connect \RD_ARST 1'0
    connect \RD_SRST 1'0
    connect \RD_ADDR { \ucode_mem_r_addr }
    connect \RD_DATA { \ucode_mem_r_data }
    connect \WR_CLK {  }
    connect \WR_EN {  }
    connect \WR_ADDR {  }
    connect \WR_DATA {  }
  end
  process $group_0
    assign \ucode_mem_r_addr 8'00000000
    assign \ucode_mem_r_addr \addr
  end
  process $group_1
    assign \fields 29'00000000000000000000000000000
    assign \fields \ucode_mem_r_data [28:0]
  end
  connect \ucode_mem_r_en 1'1
end

$ yosys -p 'read_ilang mem.rtlil; synth_lattice -family ecp5 -run :check; autoname; hierarchy -check; write_verilog foo.v'