techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes #5045
Conversation
prjtrellis documentation shows that EBR clock inputs have optional inverters. The bram techmap outputs those parameters, and nextpnr consumes them. But for whatever reason, Diamond doesn't include those parameters in its blackbox models. This makes synth_lattice fail when targeting ECP5 with a design that maps block RAMs if you include any pass that needs cells_bb_ecp5.v's definitions. This change fixes up the ECP5 bram blackbox models at generation time, by adding the missing parameters back in. Signed-off-by: David Anderson <[email protected]>
|
Another note on the approach: this is fundamentally a slight disagreement between the ground truth of what the hardware can do (as discovered by prjtrellis), and Lattice's official tools. This PR resolves the disagreement in favor of the all-OSS toolchain, which offers a superset of the configurations that the vendor tools can express. It was also the simplest fix, in that the yosys techmap, nextpnr, and prjtrellis all know that ECP5 EBRs have clock inverters, and handle them appropriately. The only holdout (and cause of this bug) is this one blackbox definition that was mechanically derived from the vendor tooling, and disagrees with the rest of the OSS ECP5 toolchain. An alternative way to fix this would be to resolve in favor of vendor tooling, and strip out CLKMUX settings from the ECP5 memory techmaps. That would make synthesis output directly compatible with Diamond place&route, and I think would still work with nextpnr as I believe it applies sensible defaults for these params. My assumption is that this compat isn't hugely compelling, because a hybrid workflow (yosys into diamond p&r) is uncommon, and mostly people stick to either the OSS toolchain or Lattice Diamond end-to-end. Plus, this is easily fixed with a post-processing script after the main synth run, if needed. I mention this just to say that if maintainer preference is to resolve in the other direction, I can make that happen too. I don't personally need these clock inverters, I just want my synthesis to work :) |
What are the reasons/motivation for this change?
Fixes #3952 , missing parameters on ECP5 EBR blackboxes.
Explain how this is achieved.
prjtrellis documentation shows that EBR clock inputs have optional inverters. The bram techmap outputs those parameters, and nextpnr consumes them. But for whatever reason, Diamond doesn't include those parameters in its blackbox models. This makes synth_lattice fail when targeting ECP5 with a design that maps block RAMs.
This change fixes up the ECP5 bram blackbox models at generation time, by adding in the missing parameters.
If applicable, please suggest to reviewers how they can test the change.
Grab this
synth.vhttps://gist.github.com/danderson/3e80ce79da41673de1ee0dff22e0e596 . The Verilog is a bit verbose, but it's just a basic 1kiB block RAM with registered output.With yosys@main:
yosys -p 'read_verilog -sv -defer synth.v; hierarchy -top mkTop; synth_lattice -family ecp5'Observe synthesis failure with error:
yosys -p 'read_verilog -sv -defer synth.v; hierarchy -top mkTop; synth_lattice -family ecp5'Observe synthesis now succeeds.
-abc9tosynth_latticebefore and after. Before:After: synthesis succeeds.