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author
Aditya Nandakumar
committed
[GlobalISel]: Fix lowering of G_Shuffle_vector where we pick up the wrong source index
https://reviews.llvm.org/D66182 llvm-svn: 368781
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2 files changed

+35
-8
lines changed

2 files changed

+35
-8
lines changed

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3824,7 +3824,6 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
38243824
LLT Src0Ty = MRI.getType(Src0Reg);
38253825
LLT DstTy = MRI.getType(DstReg);
38263826
LLT EltTy = DstTy.getElementType();
3827-
int NumElts = DstTy.getNumElements();
38283827
LLT IdxTy = LLT::scalar(32);
38293828

38303829
const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
@@ -3846,6 +3845,7 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
38463845
if (Src0Ty.isScalar()) {
38473846
BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
38483847
} else {
3848+
int NumElts = Src0Ty.getNumElements();
38493849
Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
38503850
int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
38513851
auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir

Lines changed: 34 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -182,6 +182,28 @@ body: |
182182
183183
...
184184

185+
---
186+
name: shufflevector_v3s32_3_2_1_smaller
187+
tracksRegLiveness: true
188+
189+
body: |
190+
bb.0:
191+
liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
192+
193+
; CHECK-LABEL: name: shufflevector_v3s32_3_2_1_smaller
194+
; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
195+
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
196+
; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
197+
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<3 x s32>), 64
198+
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](<3 x s32>), 32
199+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[EXTRACT]](s32), [[EXTRACT1]](s32)
200+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
201+
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
202+
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
203+
%2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(2, 1)
204+
$vgpr0_vgpr1 = COPY %2
205+
206+
...
185207
---
186208
name: shufflevector_v2s16_0_1
187209
tracksRegLiveness: true
@@ -247,7 +269,7 @@ body: |
247269
; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s16)
248270
; CHECK: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[UV2]](s16)
249271
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT]](s32), [[SEXT1]](s32), [[SEXT2]](s32)
250-
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 32
272+
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
251273
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT2]](s32)
252274
; CHECK: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
253275
; CHECK: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[UV3]](s16)
@@ -256,17 +278,22 @@ body: |
256278
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT3]](s32), [[SEXT4]](s32), [[SEXT5]](s32)
257279
; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 32
258280
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT3]](s32)
259-
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
260-
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
261-
; CHECK: [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
281+
; CHECK: [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT1]](<3 x s16>)
262282
; CHECK: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[UV6]](s16)
263283
; CHECK: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[UV7]](s16)
264284
; CHECK: [[SEXT8:%[0-9]+]]:_(s32) = G_SEXT [[UV8]](s16)
265285
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT6]](s32), [[SEXT7]](s32), [[SEXT8]](s32)
266286
; CHECK: [[EXTRACT4:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR2]](<3 x s32>), 0
267-
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT4]](s32)
268-
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
269-
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR3]](<4 x s16>)
287+
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT4]](s32)
288+
; CHECK: [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
289+
; CHECK: [[SEXT9:%[0-9]+]]:_(s32) = G_SEXT [[UV9]](s16)
290+
; CHECK: [[SEXT10:%[0-9]+]]:_(s32) = G_SEXT [[UV10]](s16)
291+
; CHECK: [[SEXT11:%[0-9]+]]:_(s32) = G_SEXT [[UV11]](s16)
292+
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT9]](s32), [[SEXT10]](s32), [[SEXT11]](s32)
293+
; CHECK: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR3]](<3 x s32>), 0
294+
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[EXTRACT5]](s32)
295+
; CHECK: [[BUILD_VECTOR4:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
296+
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR4]](<4 x s16>)
270297
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
271298
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
272299
%2:_(<3 x s16>) = G_EXTRACT %0, 0

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