11use super :: { InlineAsmArch , InlineAsmType } ;
2- // use crate::spec::Target;
2+ use crate :: spec:: Target ;
33use rustc_macros:: HashStable_Generic ;
44use std:: fmt;
55
@@ -38,11 +38,71 @@ impl XtensaInlineAsmRegClass {
3838 ) -> & ' static [ ( InlineAsmType , Option < & ' static str > ) ] {
3939 match self {
4040 Self :: reg | Self :: breg => types ! { _: I8 , I16 , I32 ; } ,
41- Self :: freg => types ! { _ : F32 ; } ,
41+ Self :: freg => types ! { "fp" : F32 ; } , // TODO how does the dfpaccel feature interact F64 types? // _:F64;
4242 }
4343 }
4444}
4545
46+ // Xtensa has lots a features - macro to reduce boiler plate
47+ macro_rules! feature {
48+ ( $fnname: ident, $feature: expr) => {
49+ fn $fnname(
50+ _arch: InlineAsmArch ,
51+ mut has_feature: impl FnMut ( & str ) -> bool ,
52+ _target: & Target ,
53+ ) -> Result <( ) , & ' static str > {
54+ if has_feature( $feature) {
55+ Ok ( ( ) )
56+ } else {
57+ Err ( concat!( "target does not support " , $feature, " registers" ) )
58+ }
59+ }
60+ } ;
61+ }
62+
63+ feature ! ( has_fp, "fp" ) ;
64+ feature ! ( has_dfpaccel, "dfpaccel" ) ;
65+ feature ! ( has_bool, "bool" ) ;
66+ feature ! ( has_loop, "loop" ) ;
67+ feature ! ( has_extendedl32r, "extendedl32r" ) ;
68+ feature ! ( has_s32c1i, "s32c1i" ) ;
69+ feature ! ( has_mac16, "mac16" ) ;
70+ feature ! ( has_windowed, "windowed" ) ;
71+ feature ! ( has_debug, "debug" ) ;
72+ feature ! ( has_memctl, "memctl" ) ;
73+ feature ! ( has_atomctl, "atomctl" ) ;
74+ feature ! ( has_exception, "exception" ) ;
75+ feature ! ( has_coprocessor, "coprocessor" ) ;
76+ feature ! ( has_rvector, "rvector" ) ;
77+ feature ! ( has_timerint, "timerint" ) ;
78+ feature ! ( has_interrupt, "interrupt" ) ;
79+ feature ! ( has_prid, "prid" ) ;
80+ feature ! ( has_miscsr, "miscsr" ) ;
81+ feature ! ( has_threadptr, "threadptr" ) ;
82+
83+ fn has_expstate (
84+ _arch : InlineAsmArch ,
85+ _has_feature : impl FnMut ( & str ) -> bool ,
86+ target : & Target ,
87+ ) -> Result < ( ) , & ' static str > {
88+ match target. cpu . as_str ( ) {
89+ "esp32" => Ok ( ( ) ) ,
90+ _ => Err ( "target does not support expstate registers" )
91+ }
92+ }
93+ fn has_gpio_out (
94+ _arch : InlineAsmArch ,
95+ _has_feature : impl FnMut ( & str ) -> bool ,
96+ target : & Target ,
97+ ) -> Result < ( ) , & ' static str > {
98+ match target. cpu . as_str ( ) {
99+ "esp32-s2" => Ok ( ( ) ) ,
100+ _ => Err ( "target does not support gpio_out registers" )
101+ }
102+ }
103+
104+
105+
46106def_regs ! {
47107 Xtensa XtensaInlineAsmReg XtensaInlineAsmRegClass {
48108 a0: reg = [ "a0" ] ,
@@ -61,114 +121,114 @@ def_regs! {
61121 a13: reg = [ "a13" ] ,
62122 a14: reg = [ "a14" ] ,
63123 a15: reg = [ "a15" ] ,
64- lbeg : reg = [ "lbeg " ] ,
65- lend : reg = [ "lend " ] ,
66- lcount : reg = [ "lcount " ] ,
67- sar : reg = [ "sar " ] ,
68- br : reg = [ "br " ] ,
69- litbase : reg = [ "litbase" ] ,
70- scompare1 : reg = [ "scompare1" ] ,
71- acclo : reg = [ "acclo" ] ,
72- acchi : reg = [ "acchi" ] ,
73- m0 : reg = [ "m0" ] ,
74- m1 : reg = [ "m1" ] ,
75- m2 : reg = [ "m2" ] ,
76- m3 : reg = [ "m3" ] ,
77- windowbase : reg = [ "windowbase" ] ,
78- windowstart : reg = [ "windowstart" ] ,
79- ibreakenable : reg = [ "ibreakenable" ] ,
80- memctl : reg = [ "memctl" ] ,
81- atomctl : reg = [ "atomctl" ] ,
82- ddr : reg = [ "ddr" ] ,
83- ibreaka0: reg = [ "ibreaka0" ] ,
84- ibreaka1: reg = [ "ibreaka1" ] ,
85- dbreaka0: reg = [ "dbreaka0" ] ,
86- dbreaka1: reg = [ "dbreaka1" ] ,
87- dbreakc0: reg = [ "dbreakc0" ] ,
88- dbreakc1: reg = [ "dbreakc1" ] ,
89- configid0 : reg = [ "configid0" ] ,
90- epc1 : reg = [ "epc1" ] ,
91- epc2 : reg = [ "epc2" ] ,
92- epc3 : reg = [ "epc3" ] ,
93- epc4 : reg = [ "epc4" ] ,
94- epc5 : reg = [ "epc5" ] ,
95- epc6 : reg = [ "epc6" ] ,
96- epc7 : reg = [ "epc7" ] ,
97- depc : reg = [ "depc" ] ,
98- eps2 : reg = [ "eps2" ] ,
99- eps3 : reg = [ "eps3" ] ,
100- eps4 : reg = [ "eps4" ] ,
101- eps5 : reg = [ "eps5" ] ,
102- eps6 : reg = [ "eps6" ] ,
103- eps7 : reg = [ "eps7" ] ,
104- configid1 : reg = [ "configid1" ] ,
105- excsave1 : reg = [ "excsave1" ] ,
106- excsave2 : reg = [ "excsave2" ] ,
107- excsave3 : reg = [ "excsave3" ] ,
108- excsave4 : reg = [ "excsave4" ] ,
109- excsave5 : reg = [ "excsave5" ] ,
110- excsave6 : reg = [ "excsave6" ] ,
111- excsave7 : reg = [ "excsave7" ] ,
112- cpenable : reg = [ "cpenable" ] ,
113- interrupt : reg = [ "interrupt" ] ,
114- intclear : reg = [ "intclear" ] ,
115- intenable : reg = [ "intenable" ] ,
116- ps : reg = [ "ps" ] ,
117- vecbase : reg = [ "vecbase" ] ,
118- exccause : reg = [ "exccause" ] ,
119- debugcause : reg = [ "debugcause" ] ,
120- ccount : reg = [ "ccount" ] ,
121- prid : reg = [ "prid" ] ,
122- icount : reg = [ "icount" ] ,
123- icountlevel : reg = [ "icountlevel" ] ,
124- excvaddr : reg = [ "excvaddr" ] ,
125- ccompare0 : reg = [ "ccompare0" ] ,
126- ccompare1 : reg = [ "ccompare1" ] ,
127- ccompare2 : reg = [ "ccompare2" ] ,
128- misc0 : reg = [ "misc0" ] ,
129- misc1 : reg = [ "misc1" ] ,
130- misc2 : reg = [ "misc2" ] ,
131- misc3 : reg = [ "misc3" ] ,
132- gpio_out : reg = [ "gpio_out" ] ,
133- expstate : reg = [ "expstate" ] ,
134- threadptr : reg = [ "threadptr" ] ,
135- fcr : reg = [ "fcr" ] ,
136- fsr : reg = [ "fsr" ] ,
137- f64r_lo : reg = [ "f64r_lo" ] ,
138- f64r_hi : reg = [ "f64r_hi" ] ,
139- f64s : reg = [ "f64s" ] ,
140- f0 : freg = [ "f0" ] ,
141- f1 : freg = [ "f1" ] ,
142- f2 : freg = [ "f2" ] ,
143- f3 : freg = [ "f3" ] ,
144- f4 : freg = [ "f4" ] ,
145- f5 : freg = [ "f5" ] ,
146- f6 : freg = [ "f6" ] ,
147- f7 : freg = [ "f7" ] ,
148- f8 : freg = [ "f8" ] ,
149- f9 : freg = [ "f9" ] ,
150- f10 : freg = [ "f10" ] ,
151- f11 : freg = [ "f11" ] ,
152- f12 : freg = [ "f12" ] ,
153- f13 : freg = [ "f13" ] ,
154- f14 : freg = [ "f14" ] ,
155- f15 : freg = [ "f15" ] ,
156- b0: breg = [ "b0" ] ,
157- b1: breg = [ "b1" ] ,
158- b2: breg = [ "b2" ] ,
159- b3: breg = [ "b3" ] ,
160- b4: breg = [ "b4" ] ,
161- b5: breg = [ "b5" ] ,
162- b6: breg = [ "b6" ] ,
163- b7: breg = [ "b7" ] ,
164- b8: breg = [ "b8" ] ,
165- b9: breg = [ "b9" ] ,
166- b10: breg = [ "b10" ] ,
167- b11: breg = [ "b11" ] ,
168- b12: breg = [ "b12" ] ,
169- b13: breg = [ "b13" ] ,
170- b14: breg = [ "b14" ] ,
171- b15: breg = [ "b15" ] ,
124+ sar : reg = [ "sar " ] , // TODO what feature enables this, if any?
125+ ddr : reg = [ "ddr " ] , // TODO what feature enables this, if any?
126+ ps : reg = [ "ps " ] , // TODO what feature enables this, if any?
127+ configid0 : reg = [ "configid0 " ] , // TODO what feature enables this, if any?
128+ configid1 : reg = [ "configid1 " ] , // TODO what feature enables this, if any?
129+ lbeg : reg = [ "lbeg" ] % has_loop ,
130+ lend : reg = [ "lend" ] % has_loop ,
131+ lcount : reg = [ "lcount" ] % has_loop ,
132+ litbase : reg = [ "litbase" ] % has_extendedl32r ,
133+ scompare1 : reg = [ "scompare1" ] % has_s32c1i ,
134+ acclo : reg = [ "acclo" ] % has_mac16 ,
135+ acchi : reg = [ "acchi" ] % has_mac16 ,
136+ m0 : reg = [ "m0" ] % has_mac16 ,
137+ m1 : reg = [ "m1" ] % has_mac16 ,
138+ m2 : reg = [ "m2" ] % has_mac16 ,
139+ m3 : reg = [ "m3" ] % has_mac16 ,
140+ windowbase : reg = [ "windowbase" ] % has_windowed ,
141+ windowstart : reg = [ "windowstart" ] % has_windowed ,
142+ ibreakenable : reg = [ "ibreakenable" ] % has_debug ,
143+ ibreaka0: reg = [ "ibreaka0" ] % has_debug ,
144+ ibreaka1: reg = [ "ibreaka1" ] % has_debug ,
145+ dbreaka0: reg = [ "dbreaka0" ] % has_debug ,
146+ dbreaka1: reg = [ "dbreaka1" ] % has_debug ,
147+ dbreakc0: reg = [ "dbreakc0" ] % has_debug ,
148+ dbreakc1: reg = [ "dbreakc1" ] % has_debug ,
149+ icount : reg = [ "icount" ] % has_debug ,
150+ icountlevel : reg = [ "icountlevel" ] % has_debug ,
151+ debugcause : reg = [ "debugcause" ] % has_debug ,
152+ memctl : reg = [ "memctl" ] % has_memctl ,
153+ atomctl : reg = [ "atomctl" ] % has_atomctl ,
154+ epc1 : reg = [ "epc1" ] % has_exception ,
155+ epc2 : reg = [ "epc2" ] % has_exception ,
156+ epc3 : reg = [ "epc3" ] % has_exception ,
157+ epc4 : reg = [ "epc4" ] % has_exception ,
158+ epc5 : reg = [ "epc5" ] % has_exception ,
159+ epc6 : reg = [ "epc6" ] % has_exception ,
160+ epc7 : reg = [ "epc7" ] % has_exception ,
161+ depc : reg = [ "depc" ] % has_exception ,
162+ eps2 : reg = [ "eps2" ] % has_exception ,
163+ eps3 : reg = [ "eps3" ] % has_exception ,
164+ eps4 : reg = [ "eps4" ] % has_exception ,
165+ eps5 : reg = [ "eps5" ] % has_exception ,
166+ eps6 : reg = [ "eps6" ] % has_exception ,
167+ eps7 : reg = [ "eps7" ] % has_exception ,
168+ excsave1 : reg = [ "excsave1" ] % has_exception ,
169+ excsave2 : reg = [ "excsave2" ] % has_exception ,
170+ excsave3 : reg = [ "excsave3" ] % has_exception ,
171+ excsave4 : reg = [ "excsave4" ] % has_exception ,
172+ excsave5 : reg = [ "excsave5" ] % has_exception ,
173+ excsave6 : reg = [ "excsave6" ] % has_exception ,
174+ excsave7 : reg = [ "excsave7" ] % has_exception ,
175+ exccause : reg = [ "exccause" ] % has_exception ,
176+ excvaddr : reg = [ "excvaddr" ] % has_exception ,
177+ cpenable : reg = [ "cpenable" ] % has_coprocessor ,
178+ vecbase : reg = [ "vecbase" ] % has_rvector ,
179+ interrupt : reg = [ "interrupt" ] % has_interrupt ,
180+ intclear : reg = [ "intclear" ] % has_interrupt ,
181+ intenable : reg = [ "intenable" ] % has_interrupt ,
182+ prid : reg = [ "prid" ] % has_prid ,
183+ ccount : reg = [ "ccount" ] % has_timerint ,
184+ ccompare0 : reg = [ "ccompare0" ] % has_timerint ,
185+ ccompare1 : reg = [ "ccompare1" ] % has_timerint ,
186+ ccompare2 : reg = [ "ccompare2" ] % has_timerint ,
187+ misc0 : reg = [ "misc0" ] % has_miscsr ,
188+ misc1 : reg = [ "misc1" ] % has_miscsr ,
189+ misc2 : reg = [ "misc2" ] % has_miscsr ,
190+ misc3 : reg = [ "misc3" ] % has_miscsr ,
191+ gpio_out : reg = [ "gpio_out" ] % has_gpio_out ,
192+ expstate : reg = [ "expstate" ] % has_expstate ,
193+ threadptr : reg = [ "threadptr" ] % has_threadptr ,
194+ fcr : reg = [ "fcr" ] % has_dfpaccel ,
195+ fsr : reg = [ "fsr" ] % has_dfpaccel ,
196+ f64r_lo : reg = [ "f64r_lo" ] % has_dfpaccel ,
197+ f64r_hi : reg = [ "f64r_hi" ] % has_dfpaccel ,
198+ f64s : reg = [ "f64s" ] % has_dfpaccel ,
199+ f0 : freg = [ "f0" ] % has_fp ,
200+ f1 : freg = [ "f1" ] % has_fp ,
201+ f2 : freg = [ "f2" ] % has_fp ,
202+ f3 : freg = [ "f3" ] % has_fp ,
203+ f4 : freg = [ "f4" ] % has_fp ,
204+ f5 : freg = [ "f5" ] % has_fp ,
205+ f6 : freg = [ "f6" ] % has_fp ,
206+ f7 : freg = [ "f7" ] % has_fp ,
207+ f8 : freg = [ "f8" ] % has_fp ,
208+ f9 : freg = [ "f9" ] % has_fp ,
209+ f10 : freg = [ "f10" ] % has_fp ,
210+ f11 : freg = [ "f11" ] % has_fp ,
211+ f12 : freg = [ "f12" ] % has_fp ,
212+ f13 : freg = [ "f13" ] % has_fp ,
213+ f14 : freg = [ "f14" ] % has_fp ,
214+ f15 : freg = [ "f15" ] % has_fp ,
215+ br : reg = [ "br" ] % has_bool ,
216+ b0: breg = [ "b0" ] % has_bool ,
217+ b1: breg = [ "b1" ] % has_bool ,
218+ b2: breg = [ "b2" ] % has_bool ,
219+ b3: breg = [ "b3" ] % has_bool ,
220+ b4: breg = [ "b4" ] % has_bool ,
221+ b5: breg = [ "b5" ] % has_bool ,
222+ b6: breg = [ "b6" ] % has_bool ,
223+ b7: breg = [ "b7" ] % has_bool ,
224+ b8: breg = [ "b8" ] % has_bool ,
225+ b9: breg = [ "b9" ] % has_bool ,
226+ b10: breg = [ "b10" ] % has_bool ,
227+ b11: breg = [ "b11" ] % has_bool ,
228+ b12: breg = [ "b12" ] % has_bool ,
229+ b13: breg = [ "b13" ] % has_bool ,
230+ b14: breg = [ "b14" ] % has_bool ,
231+ b15: breg = [ "b15" ] % has_bool ,
172232 }
173233}
174234
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