Add Xtensa asm!() esp32 target

compiler/rustc_codegen_llvm/src/asm.rs

@@ -289,6 +289,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
                 InlineAsmArch::SpirV => {}
                 InlineAsmArch::Wasm32 => {}
                 InlineAsmArch::Bpf => {}
+                InlineAsmArch::Xtensa => {}
             }
         }
         if !options.contains(InlineAsmOptions::NOMEM) {
@@ -599,6 +600,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
             InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
                 bug!("LLVM backend does not support SPIR-V")
             }
+            InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => "r",
+            InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg_bool) => "b",
+            InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => "f",
             InlineAsmRegClass::Err => unreachable!(),
         }
         .to_string(),
@@ -668,6 +672,7 @@ fn modifier_to_llvm(
         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("LLVM backend does not support SPIR-V")
         }
+        InlineAsmRegClass::Xtensa(_) => None,
         InlineAsmRegClass::Err => unreachable!(),
     }
 }
@@ -717,6 +722,9 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("LLVM backend does not support SPIR-V")
         }
+        InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => cx.type_i32(),
+        InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg_bool) => cx.type_i1(),
+        InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => cx.type_f32(),
         InlineAsmRegClass::Err => unreachable!(),
     }
 }

compiler/rustc_span/src/symbol.rs

@@ -952,6 +952,7 @@ symbols! {
         reg32,
         reg64,
         reg_abcd,
+        reg_bool,
         reg_byte,
         reg_nonzero,
         reg_thumb,

compiler/rustc_target/src/asm/mod.rs

@@ -157,6 +157,7 @@ mod riscv;
 mod spirv;
 mod wasm;
 mod x86;
+mod xtensa;
 
 pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
 pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
@@ -169,6 +170,7 @@ pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
 pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
 pub use wasm::{WasmInlineAsmReg, WasmInlineAsmRegClass};
 pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
+pub use xtensa::{XtensaInlineAsmReg, XtensaInlineAsmRegClass};
 
 #[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
 pub enum InlineAsmArch {
@@ -187,6 +189,7 @@ pub enum InlineAsmArch {
     SpirV,
     Wasm32,
     Bpf,
+    Xtensa,
 }
 
 impl FromStr for InlineAsmArch {
@@ -209,6 +212,7 @@ impl FromStr for InlineAsmArch {
             "spirv" => Ok(Self::SpirV),
             "wasm32" => Ok(Self::Wasm32),
             "bpf" => Ok(Self::Bpf),
+            "xtensa" => Ok(Self::Xtensa),
             _ => Err(()),
         }
     }
@@ -238,6 +242,7 @@ pub enum InlineAsmReg {
     SpirV(SpirVInlineAsmReg),
     Wasm(WasmInlineAsmReg),
     Bpf(BpfInlineAsmReg),
+    Xtensa(XtensaInlineAsmReg),
     // Placeholder for invalid register constraints for the current target
     Err,
 }
@@ -253,6 +258,7 @@ impl InlineAsmReg {
             Self::Hexagon(r) => r.name(),
             Self::Mips(r) => r.name(),
             Self::Bpf(r) => r.name(),
+            Self::Xtensa(r) => r.name(),
             Self::Err => "<reg>",
         }
     }
@@ -267,6 +273,7 @@ impl InlineAsmReg {
             Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
             Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
             Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
+            Self::Xtensa(r) => InlineAsmRegClass::Xtensa(r.reg_class()),
             Self::Err => InlineAsmRegClass::Err,
         }
     }
@@ -314,6 +321,9 @@ impl InlineAsmReg {
             InlineAsmArch::Bpf => {
                 Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?)
             }
+            InlineAsmArch::Xtensa => {
+                Self::Xtensa(XtensaInlineAsmReg::parse(arch, has_feature, target, &name)?)
+            }
         })
     }
 
@@ -334,6 +344,7 @@ impl InlineAsmReg {
             Self::Hexagon(r) => r.emit(out, arch, modifier),
             Self::Mips(r) => r.emit(out, arch, modifier),
             Self::Bpf(r) => r.emit(out, arch, modifier),
+            Self::Xtensa(r) => r.emit(out, arch, modifier),
             Self::Err => unreachable!("Use of InlineAsmReg::Err"),
         }
     }
@@ -348,6 +359,7 @@ impl InlineAsmReg {
             Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
             Self::Mips(_) => cb(self),
             Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
+            Self::Xtensa(r) => r.overlapping_regs(|r| cb(Self::Xtensa(r))),
             Self::Err => unreachable!("Use of InlineAsmReg::Err"),
         }
     }
@@ -377,6 +389,7 @@ pub enum InlineAsmRegClass {
     SpirV(SpirVInlineAsmRegClass),
     Wasm(WasmInlineAsmRegClass),
     Bpf(BpfInlineAsmRegClass),
+    Xtensa(XtensaInlineAsmRegClass),
     // Placeholder for invalid register constraints for the current target
     Err,
 }
@@ -395,6 +408,7 @@ impl InlineAsmRegClass {
             Self::SpirV(r) => r.name(),
             Self::Wasm(r) => r.name(),
             Self::Bpf(r) => r.name(),
+            Self::Xtensa(r) => r.name(),
             Self::Err => rustc_span::symbol::sym::reg,
         }
     }
@@ -415,6 +429,7 @@ impl InlineAsmRegClass {
             Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
             Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
             Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
+            Self::Xtensa(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Xtensa),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -442,6 +457,7 @@ impl InlineAsmRegClass {
             Self::SpirV(r) => r.suggest_modifier(arch, ty),
             Self::Wasm(r) => r.suggest_modifier(arch, ty),
             Self::Bpf(r) => r.suggest_modifier(arch, ty),
+            Self::Xtensa(r) => r.suggest_modifier(arch, ty),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -465,6 +481,7 @@ impl InlineAsmRegClass {
             Self::SpirV(r) => r.default_modifier(arch),
             Self::Wasm(r) => r.default_modifier(arch),
             Self::Bpf(r) => r.default_modifier(arch),
+            Self::Xtensa(r) => r.default_modifier(arch),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -487,6 +504,7 @@ impl InlineAsmRegClass {
             Self::SpirV(r) => r.supported_types(arch),
             Self::Wasm(r) => r.supported_types(arch),
             Self::Bpf(r) => r.supported_types(arch),
+            Self::Xtensa(r) => r.supported_types(arch),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -512,6 +530,7 @@ impl InlineAsmRegClass {
             InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
             InlineAsmArch::Wasm32 => Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?),
             InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),
+            InlineAsmArch::Xtensa => Self::Xtensa(XtensaInlineAsmRegClass::parse(arch, name)?),
         })
     }
 
@@ -530,6 +549,7 @@ impl InlineAsmRegClass {
             Self::SpirV(r) => r.valid_modifiers(arch),
             Self::Wasm(r) => r.valid_modifiers(arch),
             Self::Bpf(r) => r.valid_modifiers(arch),
+            Self::Xtensa(r) => r.valid_modifiers(arch),
             Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
         }
     }
@@ -704,5 +724,10 @@ pub fn allocatable_registers(
             bpf::fill_reg_map(arch, has_feature, target, &mut map);
             map
         }
+        InlineAsmArch::Xtensa => {
+            let mut map = xtensa::regclass_map();
+            xtensa::fill_reg_map(arch, has_feature, target, &mut map);
+            map
+        }
     }
 }

compiler/rustc_target/src/asm/xtensa.rs

@@ -0,0 +1,185 @@
+use super::{InlineAsmArch, InlineAsmType};
+use rustc_macros::HashStable_Generic;
+use std::fmt;
+
+def_reg_class! {
+    Xtensa XtensaInlineAsmRegClass {
+        reg,
+        reg_bool,
+        freg,
+    }
+}
+
+impl XtensaInlineAsmRegClass {
+    pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
+        &[]
+    }
+
+    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
+        None
+    }
+
+    pub fn suggest_modifier(
+        self,
+        _arch: InlineAsmArch,
+        _ty: InlineAsmType,
+    ) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn supported_types(
+        self,
+        _arch: InlineAsmArch,
+    ) -> &'static [(InlineAsmType, Option<&'static str>)] {
+        match self {
+            Self::reg | Self::reg_bool => types! { _: I8, I16, I32; },
+            Self::freg => types! { _: F32, F64; },
+        }
+    }
+}
+
+def_regs! {
+    Xtensa XtensaInlineAsmReg XtensaInlineAsmRegClass {
+        a0: reg = ["a0"],
+        sp: reg = ["sp", "a1"],
+        a2: reg = ["a2"],
+        a3: reg = ["a3"],
+        a4: reg = ["a4"],
+        a5: reg = ["a5"],
+        a6: reg = ["a6"],
+        a7: reg = ["a7"],
+        a8: reg = ["a8"],
+        a9: reg = ["a9"],
+        a10: reg = ["a10"],
+        a11: reg = ["a11"],
+        a12: reg = ["a12"],
+        a13: reg = ["a13"],
+        a14: reg = ["a14"],
+        a15: reg = ["a15"],
+        lbeg: reg = ["lbeg"],
+        lend: reg = ["lend"],
+        lcount: reg = ["lcount"],
+        sar: reg = ["sar"],
+        br: reg = ["br"],
+        litbase: reg = ["litbase"],
+        scompare1: reg = ["scompare1"],
+        acclo: reg = ["acclo"],
+        acchi: reg = ["acchi"],
+        m0: reg = ["m0"],
+        m1: reg = ["m1"],
+        m2: reg = ["m2"],
+        m3: reg = ["m3"],
+        windowbase: reg = ["windowbase"],
+        windowstart: reg = ["windowstart"],
+        ibreakenable: reg = ["ibreakenable"],
+        memctl: reg = ["memctl"],
+        atomctl: reg = ["atomctl"],
+        ddr: reg = ["ddr"],
+        ibreaka0: reg = ["ibreaka0"],
+        ibreaka1: reg = ["ibreaka1"],
+        dbreaka0: reg = ["dbreaka0"],
+        dbreaka1: reg = ["dbreaka1"],
+        dbreakc0: reg = ["dbreakc0"],
+        dbreakc1: reg = ["dbreakc1"],
+        configid0: reg = ["configid0"],
+        epc1: reg = ["epc1"],
+        epc2: reg = ["epc2"],
+        epc3: reg = ["epc3"],
+        epc4: reg = ["epc4"],
+        epc5: reg = ["epc5"],
+        epc6: reg = ["epc6"],
+        epc7: reg = ["epc7"],
+        depc: reg = ["depc"],
+        eps2: reg = ["eps2"],
+        eps3: reg = ["eps3"],
+        eps4: reg = ["eps4"],
+        eps5: reg = ["eps5"],
+        eps6: reg = ["eps6"],
+        eps7: reg = ["eps7"],
+        configid1: reg = ["configid1"],
+        excsave1: reg = ["excsave1"],
+        excsave2: reg = ["excsave2"],
+        excsave3: reg = ["excsave3"],
+        excsave4: reg = ["excsave4"],
+        excsave5: reg = ["excsave5"],
+        excsave6: reg = ["excsave6"],
+        excsave7: reg = ["excsave7"],
+        cpenable: reg = ["cpenable"],
+        interrupt: reg = ["interrupt"],
+        intclear: reg = ["intclear"],
+        intenable: reg = ["intenable"],
+        ps: reg = ["ps"],
+        vecbase: reg = ["vecbase"],
+        exccause: reg = ["exccause"],
+        debugcause: reg = ["debugcause"],
+        ccount: reg = ["ccount"],
+        prid: reg = ["prid"],
+        icount: reg = ["icount"],
+        icountlevel: reg = ["icountlevel"],
+        excvaddr: reg = ["excvaddr"],
+        ccompare0: reg = ["ccompare0"],
+        ccompare1: reg = ["ccompare1"],
+        ccompare2: reg = ["ccompare2"],
+        misc0: reg = ["misc0"],
+        misc1: reg = ["misc1"],
+        misc2: reg = ["misc2"],
+        misc3: reg = ["misc3"],
+        gpio_out: reg = ["gpio_out"],
+        expstate: reg = ["expstate"],
+        threadptr: reg = ["threadptr"],
+        fcr: reg = ["fcr"],
+        fsr: reg = ["fsr"],
+        f64r_lo: reg = ["f64r_lo"],
+        f64r_hi: reg = ["f64r_hi"],
+        f64s: reg = ["f64s"],
+        f0: freg = ["f0"],
+        f1: freg = ["f1"],
+        f2: freg = ["f2"],
+        f3: freg = ["f3"],
+        f4: freg = ["f4"],
+        f5: freg = ["f5"],
+        f6: freg = ["f6"],
+        f7: freg = ["f7"],
+        f8: freg = ["f8"],
+        f9: freg = ["f9"],
+        f10: freg = ["f10"],
+        f11: freg = ["f11"],
+        f12: freg = ["f12"],
+        f13: freg = ["f13"],
+        f14: freg = ["f14"],
+        f15: freg = ["f15"],
+        b0: reg_bool = ["b0"],
+        b1: reg_bool = ["b1"],
+        b2: reg_bool = ["b2"],
+        b3: reg_bool = ["b3"],
+        b4: reg_bool = ["b4"],
+        b5: reg_bool = ["b5"],
+        b6: reg_bool = ["b6"],
+        b7: reg_bool = ["b7"],
+        b8: reg_bool = ["b8"],
+        b9: reg_bool = ["b9"],
+        b10: reg_bool = ["b10"],
+        b11: reg_bool = ["b11"],
+        b12: reg_bool = ["b12"],
+        b13: reg_bool = ["b13"],
+        b14: reg_bool = ["b14"],
+        b15: reg_bool = ["b15"],
+    }
+}
+
+impl XtensaInlineAsmReg {
+    pub fn emit(
+        self,
+        out: &mut dyn fmt::Write,
+        _arch: InlineAsmArch,
+        _modifier: Option<char>,
+    ) -> fmt::Result {
+        out.write_str(self.name())
+    }
+
+    pub fn overlapping_regs(self, mut _cb: impl FnMut(XtensaInlineAsmReg)) {}
+}