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Disable non-IRAM ISRs while cache is disabled #3579

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@igrr

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@igrr

A lot of issues with interrupt handlers occur because interrupt handler code happens to be placed into cache. Cache is not accessible while flash is read/written. This causes illegal instruction exceptions which are hard to understand and debug for many users.

Investigate if it is possible to automatically disable interrupts which have ISRs not in IRAM, while flash cache is disabled (similar to the approach used in ESP32 SDK).

If not possible, as minimum, sanity-check all ISR handler function pointers and assert when function pointer is not in IRAM.

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