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Resolve HWDT Reset with core_esp8266_vm #9025

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Merged
merged 3 commits into from
Nov 12, 2023
Merged

Resolve HWDT Reset with core_esp8266_vm #9025

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705fe49
Resolve HWDT Reset with core_esp8266_vm
mhightower83 Nov 10, 2023
b535c4f
Merge branch 'master' into pr-external-vm-fix
mhightower83 Nov 10, 2023
ecf156e
Added memory barrier to changes
mhightower83 Nov 11, 2023
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7 changes: 4 additions & 3 deletions cores/esp8266/core_esp8266_vm.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -161,20 +161,21 @@ static struct cache_line *__vm_cache; // Always points to MRU (hence the line be

constexpr int addrmask = ~(sizeof(__vm_cache[0].w)-1); // Helper to mask off bits present in cache entry


static void spi_init(spi_regs *spi1)
{
pinMode(sck, SPECIAL);
pinMode(miso, SPECIAL);
pinMode(mosi, SPECIAL);
pinMode(cs, SPECIAL);
spi1->spi_cmd = 0;
// spi_ctrl appears to need setting before other SPI registers
spi1->spi_ctrl = 0; // MSB first + plain SPI mode
asm("" ::: "memory");
GPMUX &= ~(1 << 9);
spi1->spi_clock = spi_clkval;
spi1->spi_ctrl = 0 ; // MSB first + plain SPI mode
spi1->spi_ctrl1 = 0; // undocumented, clear for safety?
spi1->spi_ctrl2 = 0; // No add'l delays on signals
spi1->spi_user2 = 0; // No insn or insn_bits to set
spi1->spi_cmd = 0;
}

// Note: GCC optimization -O2 and -O3 tried and returned *slower* code than the default
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