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fix(uart): Sets XTAL as clock source for uart #10087

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Merged
merged 10 commits into from
Aug 1, 2024
Merged

fix(uart): Sets XTAL as clock source for uart #10087

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d129308
fix(uart): Sets XTAL as clock source for uart
SuGlider Jul 30, 2024
4f1a39d
fix(typo): Typo and commentaries
SuGlider Jul 30, 2024
0a885fd
Merge branch 'master' into c6h2_lightsleep_uart_issue
SuGlider Jul 31, 2024
6cf3d68
fix(uart): adjust get/set baudrate
SuGlider Jul 31, 2024
357db7c
Merge branch 'master' into c6h2_lightsleep_uart_issue
SuGlider Jul 31, 2024
a9082d4
fix(uart): uses REF_TICK for ESP32/S2
SuGlider Jul 31, 2024
3dd24fb
fix(uart): esp32/s2 baudrate > 1MHz
SuGlider Jul 31, 2024
ac6e029
Merge branch 'master' into c6h2_lightsleep_uart_issue
SuGlider Jul 31, 2024
e082695
fix(uart): rxTimeout minimum
SuGlider Jul 31, 2024
854111f
ci(pre-commit): Apply automatic fixes
pre-commit-ci-lite[bot] Aug 1, 2024
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12 changes: 9 additions & 3 deletions cores/esp32/esp32-hal-uart.c
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Original file line number Diff line number Diff line change
Expand Up @@ -503,9 +503,15 @@ uart_t *uartBegin(
uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
uart_config.rx_flow_ctrl_thresh = rxfifo_full_thrhd;
uart_config.baud_rate = baudrate;
// CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6
uart_config.source_clk = UART_SCLK_DEFAULT;

// there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
// therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
#if SOC_UART_SUPPORT_XTAL_CLK
uart_config.source_clk = UART_SCLK_XTAL; // valid for S3, C3, C6, H2 and P4
#else
// Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6
uart_config.source_clk = UART_SCLK_DEFAULT; // valid for ESP32 and S2
#endif

UART_MUTEX_LOCK();
bool retCode = ESP_OK == uart_driver_install(uart_nr, rx_buffer_size, tx_buffer_size, 20, &(uart->uart_event_queue), 0);

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