Skip to content

Commit 5415528

Browse files
hiradityahiraditya
authored
Revert "[CodeGen] Update for scalable MemoryType in MMO (#70452)"
This reverts commit 57146da.
1 parent 6331024 commit 5415528

17 files changed

+118
-165
lines changed

‎llvm/include/llvm/Analysis/MemoryLocation.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -297,6 +297,13 @@ class MemoryLocation {
297297
return MemoryLocation(Ptr, LocationSize::beforeOrAfterPointer(), AATags);
298298
}
299299

300+
// Return the exact size if the exact size is known at compiletime,
301+
// otherwise return LocationSize::beforeOrAfterPointer().
302+
static LocationSize getSizeOrUnknown(const TypeSize &T) {
303+
return T.isScalable() ? LocationSize::beforeOrAfterPointer()
304+
: LocationSize::precise(T.getFixedValue());
305+
}
306+
300307
MemoryLocation() : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()) {}
301308

302309
explicit MemoryLocation(const Value *Ptr, LocationSize Size,

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1060,9 +1060,8 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10601060
int64_t Offset, LocationSize Size) {
10611061
return getMachineMemOperand(
10621062
MMO, Offset,
1063-
!Size.hasValue() ? LLT()
1064-
: Size.isScalable()
1065-
? LLT::scalable_vector(1, 8 * Size.getValue().getKnownMinValue())
1063+
!Size.hasValue() || Size.isScalable()
1064+
? LLT()
10661065
: LLT::scalar(8 * Size.getValue().getKnownMinValue()));
10671066
}
10681067
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,

‎llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp

Lines changed: 9 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -128,14 +128,14 @@ bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1,
128128
// vector objects on the stack.
129129
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
130130
// following situations arise:
131-
if (PtrDiff >= 0 && Size1.hasValue() && !Size1.isScalable()) {
131+
if (PtrDiff >= 0 && Size1.hasValue()) {
132132
// [----BasePtr0----]
133133
// [---BasePtr1--]
134134
// ========PtrDiff========>
135135
IsAlias = !((int64_t)Size1.getValue() <= PtrDiff);
136136
return true;
137137
}
138-
if (PtrDiff < 0 && Size2.hasValue() && !Size2.isScalable()) {
138+
if (PtrDiff < 0 && Size2.hasValue()) {
139139
// [----BasePtr0----]
140140
// [---BasePtr1--]
141141
// =====(-PtrDiff)====>
@@ -248,20 +248,10 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
248248
return false;
249249
}
250250

251-
// If NumBytes is scalable and offset is not 0, conservatively return may
252-
// alias
253-
if ((MUC0.NumBytes.isScalable() && MUC0.Offset != 0) ||
254-
(MUC1.NumBytes.isScalable() && MUC1.Offset != 0))
255-
return true;
256-
257-
const bool BothNotScalable =
258-
!MUC0.NumBytes.isScalable() && !MUC1.NumBytes.isScalable();
259-
260251
// Try to prove that there is aliasing, or that there is no aliasing. Either
261252
// way, we can return now. If nothing can be proved, proceed with more tests.
262253
bool IsAlias;
263-
if (BothNotScalable &&
264-
GISelAddressing::aliasIsKnownForLoadStore(MI, Other, IsAlias, MRI))
254+
if (GISelAddressing::aliasIsKnownForLoadStore(MI, Other, IsAlias, MRI))
265255
return IsAlias;
266256

267257
// The following all rely on MMO0 and MMO1 being valid.
@@ -277,18 +267,12 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
277267
Size1.hasValue()) {
278268
// Use alias analysis information.
279269
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
280-
int64_t Overlap0 =
281-
Size0.getValue().getKnownMinValue() + SrcValOffset0 - MinOffset;
282-
int64_t Overlap1 =
283-
Size1.getValue().getKnownMinValue() + SrcValOffset1 - MinOffset;
284-
LocationSize Loc0 =
285-
Size0.isScalable() ? Size0 : LocationSize::precise(Overlap0);
286-
LocationSize Loc1 =
287-
Size1.isScalable() ? Size1 : LocationSize::precise(Overlap1);
288-
289-
if (AA->isNoAlias(
290-
MemoryLocation(MUC0.MMO->getValue(), Loc0, MUC0.MMO->getAAInfo()),
291-
MemoryLocation(MUC1.MMO->getValue(), Loc1, MUC1.MMO->getAAInfo())))
270+
int64_t Overlap0 = Size0.getValue() + SrcValOffset0 - MinOffset;
271+
int64_t Overlap1 = Size1.getValue() + SrcValOffset1 - MinOffset;
272+
if (AA->isNoAlias(MemoryLocation(MUC0.MMO->getValue(), Overlap0,
273+
MUC0.MMO->getAAInfo()),
274+
MemoryLocation(MUC1.MMO->getValue(), Overlap1,
275+
MUC1.MMO->getAAInfo())))
292276
return false;
293277
}
294278

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 10 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1323,7 +1323,6 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13231323
LocationSize WidthB = MMOb->getSize();
13241324
bool KnownWidthA = WidthA.hasValue();
13251325
bool KnownWidthB = WidthB.hasValue();
1326-
bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();
13271326

13281327
const Value *ValA = MMOa->getValue();
13291328
const Value *ValB = MMOb->getValue();
@@ -1339,14 +1338,12 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13391338
SameVal = true;
13401339
}
13411340

1342-
if (SameVal && BothMMONonScalable) {
1341+
if (SameVal) {
13431342
if (!KnownWidthA || !KnownWidthB)
13441343
return true;
13451344
int64_t MaxOffset = std::max(OffsetA, OffsetB);
1346-
int64_t LowWidth = (MinOffset == OffsetA)
1347-
? WidthA.getValue().getKnownMinValue()
1348-
: WidthB.getValue().getKnownMinValue();
1349-
return (MinOffset + LowWidth > MaxOffset);
1345+
LocationSize LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1346+
return (MinOffset + (int)LowWidth.getValue() > MaxOffset);
13501347
}
13511348

13521349
if (!AA)
@@ -1358,29 +1355,15 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13581355
assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
13591356
assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
13601357

1361-
// If Scalable Location Size has non-zero offset, Width + Offset does not work
1362-
// at the moment
1363-
if ((WidthA.isScalable() && OffsetA > 0) ||
1364-
(WidthB.isScalable() && OffsetB > 0))
1365-
return true;
1366-
1367-
int64_t OverlapA =
1368-
KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset
1369-
: MemoryLocation::UnknownSize;
1370-
int64_t OverlapB =
1371-
KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset
1372-
: MemoryLocation::UnknownSize;
1373-
1374-
LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)
1375-
? WidthA
1376-
: LocationSize::precise(OverlapA);
1377-
LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)
1378-
? WidthB
1379-
: LocationSize::precise(OverlapB);
1358+
int64_t OverlapA = KnownWidthA ? WidthA.getValue() + OffsetA - MinOffset
1359+
: MemoryLocation::UnknownSize;
1360+
int64_t OverlapB = KnownWidthB ? WidthB.getValue() + OffsetB - MinOffset
1361+
: MemoryLocation::UnknownSize;
13801362

13811363
return !AA->isNoAlias(
1382-
MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1383-
MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1364+
MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1365+
MemoryLocation(ValB, OverlapB,
1366+
UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
13841367
}
13851368

13861369
bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,

‎llvm/lib/CodeGen/MachineOperand.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1107,13 +1107,12 @@ MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags F,
11071107
const MDNode *Ranges, SyncScope::ID SSID,
11081108
AtomicOrdering Ordering,
11091109
AtomicOrdering FailureOrdering)
1110-
: MachineMemOperand(
1111-
ptrinfo, F,
1112-
!TS.hasValue() ? LLT()
1113-
: TS.isScalable()
1114-
? LLT::scalable_vector(1, 8 * TS.getValue().getKnownMinValue())
1115-
: LLT::scalar(8 * TS.getValue().getKnownMinValue()),
1116-
BaseAlignment, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1110+
: MachineMemOperand(ptrinfo, F,
1111+
!TS.hasValue() || TS.isScalable()
1112+
? LLT()
1113+
: LLT::scalar(8 * TS.getValue().getKnownMinValue()),
1114+
BaseAlignment, AAInfo, Ranges, SSID, Ordering,
1115+
FailureOrdering) {}
11171116

11181117
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
11191118
// The Value and Offset may differ due to CSE. But the flags and size

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 19 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -24266,7 +24266,7 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
2426624266
// TODO: Use "BaseIndexOffset" to make this more effective.
2426724267
SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(), Offset, DL);
2426824268

24269-
LocationSize StoreSize = LocationSize::precise(VT.getStoreSize());
24269+
LocationSize StoreSize = MemoryLocation::getSizeOrUnknown(VT.getStoreSize());
2427024270
MachineFunction &MF = DAG.getMachineFunction();
2427124271
MachineMemOperand *MMO;
2427224272
if (Offset.isScalable()) {
@@ -27933,10 +27933,14 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2793327933
: (LSN->getAddressingMode() == ISD::PRE_DEC)
2793427934
? -1 * C->getSExtValue()
2793527935
: 0;
27936-
TypeSize Size = LSN->getMemoryVT().getStoreSize();
27937-
return {LSN->isVolatile(), LSN->isAtomic(),
27938-
LSN->getBasePtr(), Offset /*base offset*/,
27939-
LocationSize::precise(Size), LSN->getMemOperand()};
27936+
LocationSize Size =
27937+
MemoryLocation::getSizeOrUnknown(LSN->getMemoryVT().getStoreSize());
27938+
return {LSN->isVolatile(),
27939+
LSN->isAtomic(),
27940+
LSN->getBasePtr(),
27941+
Offset /*base offset*/,
27942+
Size,
27943+
LSN->getMemOperand()};
2794027944
}
2794127945
if (const auto *LN = cast<LifetimeSDNode>(N))
2794227946
return {false /*isVolatile*/,
@@ -27978,13 +27982,6 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2797827982
return false;
2797927983
}
2798027984

27981-
// If NumBytes is scalable and offset is not 0, conservatively return may
27982-
// alias
27983-
if ((MUC0.NumBytes.hasValue() && MUC0.NumBytes.isScalable() &&
27984-
MUC0.Offset != 0) ||
27985-
(MUC1.NumBytes.hasValue() && MUC1.NumBytes.isScalable() &&
27986-
MUC1.Offset != 0))
27987-
return true;
2798827985
// Try to prove that there is aliasing, or that there is no aliasing. Either
2798927986
// way, we can return now. If nothing can be proved, proceed with more tests.
2799027987
bool IsAlias;
@@ -28015,22 +28012,18 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2801528012
Align OrigAlignment1 = MUC1.MMO->getBaseAlign();
2801628013
LocationSize Size0 = MUC0.NumBytes;
2801728014
LocationSize Size1 = MUC1.NumBytes;
28018-
2801928015
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
28020-
Size0.hasValue() && Size1.hasValue() && !Size0.isScalable() &&
28021-
!Size1.isScalable() && Size0 == Size1 &&
28022-
OrigAlignment0 > Size0.getValue().getKnownMinValue() &&
28023-
SrcValOffset0 % Size0.getValue().getKnownMinValue() == 0 &&
28024-
SrcValOffset1 % Size1.getValue().getKnownMinValue() == 0) {
28016+
Size0.hasValue() && Size1.hasValue() && Size0 == Size1 &&
28017+
OrigAlignment0 > Size0.getValue() &&
28018+
SrcValOffset0 % Size0.getValue() == 0 &&
28019+
SrcValOffset1 % Size1.getValue() == 0) {
2802528020
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
2802628021
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
2802728022

2802828023
// There is no overlap between these relatively aligned accesses of
2802928024
// similar size. Return no alias.
28030-
if ((OffAlign0 + static_cast<int64_t>(
28031-
Size0.getValue().getKnownMinValue())) <= OffAlign1 ||
28032-
(OffAlign1 + static_cast<int64_t>(
28033-
Size1.getValue().getKnownMinValue())) <= OffAlign0)
28025+
if ((OffAlign0 + (int64_t)Size0.getValue()) <= OffAlign1 ||
28026+
(OffAlign1 + (int64_t)Size1.getValue()) <= OffAlign0)
2803428027
return false;
2803528028
}
2803628029

@@ -28047,18 +28040,12 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2804728040
Size0.hasValue() && Size1.hasValue()) {
2804828041
// Use alias analysis information.
2804928042
int64_t MinOffset = std::min(SrcValOffset0, SrcValOffset1);
28050-
int64_t Overlap0 =
28051-
Size0.getValue().getKnownMinValue() + SrcValOffset0 - MinOffset;
28052-
int64_t Overlap1 =
28053-
Size1.getValue().getKnownMinValue() + SrcValOffset1 - MinOffset;
28054-
LocationSize Loc0 =
28055-
Size0.isScalable() ? Size0 : LocationSize::precise(Overlap0);
28056-
LocationSize Loc1 =
28057-
Size1.isScalable() ? Size1 : LocationSize::precise(Overlap1);
28043+
int64_t Overlap0 = Size0.getValue() + SrcValOffset0 - MinOffset;
28044+
int64_t Overlap1 = Size1.getValue() + SrcValOffset1 - MinOffset;
2805828045
if (AA->isNoAlias(
28059-
MemoryLocation(MUC0.MMO->getValue(), Loc0,
28046+
MemoryLocation(MUC0.MMO->getValue(), Overlap0,
2806028047
UseTBAA ? MUC0.MMO->getAAInfo() : AAMDNodes()),
28061-
MemoryLocation(MUC1.MMO->getValue(), Loc1,
28048+
MemoryLocation(MUC1.MMO->getValue(), Overlap1,
2806228049
UseTBAA ? MUC1.MMO->getAAInfo() : AAMDNodes())))
2806328050
return false;
2806428051
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8465,7 +8465,9 @@ SDValue SelectionDAG::getMemIntrinsicNode(
84658465
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
84668466
MachineMemOperand::Flags Flags, LocationSize Size,
84678467
const AAMDNodes &AAInfo) {
8468-
if (Size.hasValue() && !Size.getValue())
8468+
if (Size.hasValue() && MemVT.isScalableVector())
8469+
Size = LocationSize::beforeOrAfterPointer();
8470+
else if (Size.hasValue() && !Size.getValue())
84698471
Size = LocationSize::precise(MemVT.getStoreSize());
84708472

84718473
MachineFunction &MF = getMachineFunction();
@@ -8628,7 +8630,7 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
86288630
if (PtrInfo.V.isNull())
86298631
PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
86308632

8631-
LocationSize Size = LocationSize::precise(MemVT.getStoreSize());
8633+
LocationSize Size = MemoryLocation::getSizeOrUnknown(MemVT.getStoreSize());
86328634
MachineFunction &MF = getMachineFunction();
86338635
MachineMemOperand *MMO = MF.getMachineMemOperand(PtrInfo, MMOFlags, Size,
86348636
Alignment, AAInfo, Ranges);
@@ -8749,7 +8751,8 @@ SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,
87498751
PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr);
87508752

87518753
MachineFunction &MF = getMachineFunction();
8752-
LocationSize Size = LocationSize::precise(Val.getValueType().getStoreSize());
8754+
LocationSize Size =
8755+
MemoryLocation::getSizeOrUnknown(Val.getValueType().getStoreSize());
87538756
MachineMemOperand *MMO =
87548757
MF.getMachineMemOperand(PtrInfo, MMOFlags, Size, Alignment, AAInfo);
87558758
return getStore(Chain, dl, Val, Ptr, MMO);
@@ -8802,8 +8805,8 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
88028805

88038806
MachineFunction &MF = getMachineFunction();
88048807
MachineMemOperand *MMO = MF.getMachineMemOperand(
8805-
PtrInfo, MMOFlags, LocationSize::precise(SVT.getStoreSize()), Alignment,
8806-
AAInfo);
8808+
PtrInfo, MMOFlags, MemoryLocation::getSizeOrUnknown(SVT.getStoreSize()),
8809+
Alignment, AAInfo);
88078810
return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO);
88088811
}
88098812

@@ -8897,7 +8900,7 @@ SDValue SelectionDAG::getLoadVP(
88978900
if (PtrInfo.V.isNull())
88988901
PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset);
88998902

8900-
LocationSize Size = LocationSize::precise(MemVT.getStoreSize());
8903+
LocationSize Size = MemoryLocation::getSizeOrUnknown(MemVT.getStoreSize());
89018904
MachineFunction &MF = getMachineFunction();
89028905
MachineMemOperand *MMO = MF.getMachineMemOperand(PtrInfo, MMOFlags, Size,
89038906
Alignment, AAInfo, Ranges);
@@ -9050,8 +9053,8 @@ SDValue SelectionDAG::getTruncStoreVP(SDValue Chain, const SDLoc &dl,
90509053

90519054
MachineFunction &MF = getMachineFunction();
90529055
MachineMemOperand *MMO = MF.getMachineMemOperand(
9053-
PtrInfo, MMOFlags, LocationSize::precise(SVT.getStoreSize()), Alignment,
9054-
AAInfo);
9056+
PtrInfo, MMOFlags, MemoryLocation::getSizeOrUnknown(SVT.getStoreSize()),
9057+
Alignment, AAInfo);
90559058
return getTruncStoreVP(Chain, dl, Val, Ptr, Mask, EVL, SVT, MMO,
90569059
IsCompressing);
90579060
}
@@ -11792,9 +11795,10 @@ MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1179211795
// We check here that the size of the memory operand fits within the size of
1179311796
// the MMO. This is because the MMO might indicate only a possible address
1179411797
// range instead of specifying the affected memory addresses precisely.
11798+
// TODO: Make MachineMemOperands aware of scalable vectors.
1179511799
assert(
1179611800
(!MMO->getType().isValid() ||
11797-
TypeSize::isKnownLE(memvt.getStoreSize(), MMO->getSize().getValue())) &&
11801+
memvt.getStoreSize().getKnownMinValue() <= MMO->getSize().getValue()) &&
1179811802
"Size mismatch!");
1179911803
}
1180011804

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,8 @@ bool BaseIndexOffset::computeAliasing(const SDNode *Op0,
106106
int64_t PtrDiff;
107107
if (BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) {
108108
// If the size of memory access is unknown, do not use it to analysis.
109+
// One example of unknown size memory access is to load/store scalable
110+
// vector objects on the stack.
109111
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
110112
// following situations arise:
111113
if (PtrDiff >= 0 && NumBytes0.hasValue() && !NumBytes0.isScalable()) {

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4974,8 +4974,7 @@ void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
49744974
unsigned AS = Ptr->getType()->getScalarType()->getPointerAddressSpace();
49754975
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
49764976
MachinePointerInfo(AS), MachineMemOperand::MOLoad,
4977-
LocationSize::beforeOrAfterPointer(), Alignment, I.getAAMetadata(),
4978-
Ranges);
4977+
LocationSize::beforeOrAfterPointer(), Alignment, I.getAAMetadata(), Ranges);
49794978

49804979
if (!UniformBase) {
49814980
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2687,7 +2687,10 @@ bool AArch64InstrInfo::getMemOperandsWithOffsetWidth(
26872687
return false;
26882688
// The maximum vscale is 16 under AArch64, return the maximal extent for the
26892689
// vector.
2690-
Width = LocationSize::precise(WidthN);
2690+
Width = WidthN.isScalable()
2691+
? WidthN.getKnownMinValue() * AArch64::SVEMaxBitsPerVector /
2692+
AArch64::SVEBitsPerBlock
2693+
: WidthN.getKnownMinValue();
26912694
BaseOps.push_back(BaseOp);
26922695
return true;
26932696
}

0 commit comments

Comments
 (0)