Skip to content

Commit 6670226

Browse files
bjopeyuxuanchen1997
bjope
authored and
yuxuanchen1997
committed
[DAGCombiner] Push freeze through SETCC and SELECT_CC (#64718)
Summary: Allow pushing freeze through SETCC and SELECT_CC even if there are multiple "maybe poison" operands. In the past we have limited it to a single "maybe poison" operand, but it seems profitable to also allow the multiple operand scenario. One goal here is to avoid some regressions seen in review of #84924 when solving the select->and miscompiles described in #84653 Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251168
1 parent 995dd98 commit 6670226

File tree

3 files changed

+87
-92
lines changed

3 files changed

+87
-92
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15653,6 +15653,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
1565315653
return SDValue();
1565415654

1565515655
bool AllowMultipleMaybePoisonOperands =
15656+
N0.getOpcode() == ISD::SELECT_CC ||
15657+
N0.getOpcode() == ISD::SETCC ||
1565615658
N0.getOpcode() == ISD::BUILD_VECTOR ||
1565715659
N0.getOpcode() == ISD::BUILD_PAIR ||
1565815660
N0.getOpcode() == ISD::VECTOR_SHUFFLE ||

‎llvm/test/CodeGen/RISCV/double-convert.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -742,9 +742,8 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
742742
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
743743
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
744744
; RV32IZFINXZDINX-NEXT: lui a5, 524288
745-
; RV32IZFINXZDINX-NEXT: li a4, 1
746745
; RV32IZFINXZDINX-NEXT: lui a3, 524288
747-
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB12_2
746+
; RV32IZFINXZDINX-NEXT: beqz a2, .LBB12_2
748747
; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
749748
; RV32IZFINXZDINX-NEXT: mv a3, a1
750749
; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start

‎llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

Lines changed: 84 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -102,30 +102,29 @@ define i64 @test_floor_si64(double %x) nounwind {
102102
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
103103
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2)
104104
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
105-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
105+
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI1_1)
106+
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI1_1+4)(a4)
107+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a4)
108+
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
109+
; RV32IZFINXZDINX-NEXT: neg a2, a6
110+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
111+
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
112+
; RV32IZFINXZDINX-NEXT: neg a2, a4
113+
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
114+
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
115+
; RV32IZFINXZDINX-NEXT: neg a2, a2
106116
; RV32IZFINXZDINX-NEXT: lui a5, 524288
107-
; RV32IZFINXZDINX-NEXT: li a4, 1
108117
; RV32IZFINXZDINX-NEXT: lui a3, 524288
109-
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB1_2
118+
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB1_2
110119
; RV32IZFINXZDINX-NEXT: # %bb.1:
111120
; RV32IZFINXZDINX-NEXT: mv a3, a1
112121
; RV32IZFINXZDINX-NEXT: .LBB1_2:
113-
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI1_1)
114-
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI1_1)(a1)
115-
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI1_1+4)(a1)
116-
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
122+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
117123
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB1_4
118124
; RV32IZFINXZDINX-NEXT: # %bb.3:
119125
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
120126
; RV32IZFINXZDINX-NEXT: .LBB1_4:
121-
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
122-
; RV32IZFINXZDINX-NEXT: neg a5, a1
123-
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
124-
; RV32IZFINXZDINX-NEXT: neg a2, a2
125-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
126-
; RV32IZFINXZDINX-NEXT: neg a2, a4
127-
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
128-
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
127+
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
129128
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
130129
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
131130
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -347,30 +346,29 @@ define i64 @test_ceil_si64(double %x) nounwind {
347346
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_0)
348347
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI5_0+4)(a2)
349348
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_0)(a2)
350-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
349+
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI5_1)
350+
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI5_1+4)(a4)
351+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI5_1)(a4)
352+
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
353+
; RV32IZFINXZDINX-NEXT: neg a2, a6
354+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
355+
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
356+
; RV32IZFINXZDINX-NEXT: neg a2, a4
357+
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
358+
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
359+
; RV32IZFINXZDINX-NEXT: neg a2, a2
351360
; RV32IZFINXZDINX-NEXT: lui a5, 524288
352-
; RV32IZFINXZDINX-NEXT: li a4, 1
353361
; RV32IZFINXZDINX-NEXT: lui a3, 524288
354-
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB5_2
362+
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB5_2
355363
; RV32IZFINXZDINX-NEXT: # %bb.1:
356364
; RV32IZFINXZDINX-NEXT: mv a3, a1
357365
; RV32IZFINXZDINX-NEXT: .LBB5_2:
358-
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI5_1)
359-
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI5_1)(a1)
360-
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI5_1+4)(a1)
361-
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
366+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
362367
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB5_4
363368
; RV32IZFINXZDINX-NEXT: # %bb.3:
364369
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
365370
; RV32IZFINXZDINX-NEXT: .LBB5_4:
366-
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
367-
; RV32IZFINXZDINX-NEXT: neg a5, a1
368-
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
369-
; RV32IZFINXZDINX-NEXT: neg a2, a2
370-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
371-
; RV32IZFINXZDINX-NEXT: neg a2, a4
372-
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
373-
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
371+
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
374372
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
375373
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
376374
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -592,30 +590,29 @@ define i64 @test_trunc_si64(double %x) nounwind {
592590
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI9_0)
593591
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI9_0+4)(a2)
594592
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI9_0)(a2)
595-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
593+
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI9_1)
594+
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI9_1+4)(a4)
595+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI9_1)(a4)
596+
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
597+
; RV32IZFINXZDINX-NEXT: neg a2, a6
598+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
599+
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
600+
; RV32IZFINXZDINX-NEXT: neg a2, a4
601+
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
602+
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
603+
; RV32IZFINXZDINX-NEXT: neg a2, a2
596604
; RV32IZFINXZDINX-NEXT: lui a5, 524288
597-
; RV32IZFINXZDINX-NEXT: li a4, 1
598605
; RV32IZFINXZDINX-NEXT: lui a3, 524288
599-
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB9_2
606+
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB9_2
600607
; RV32IZFINXZDINX-NEXT: # %bb.1:
601608
; RV32IZFINXZDINX-NEXT: mv a3, a1
602609
; RV32IZFINXZDINX-NEXT: .LBB9_2:
603-
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI9_1)
604-
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI9_1)(a1)
605-
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI9_1+4)(a1)
606-
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
610+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
607611
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB9_4
608612
; RV32IZFINXZDINX-NEXT: # %bb.3:
609613
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
610614
; RV32IZFINXZDINX-NEXT: .LBB9_4:
611-
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
612-
; RV32IZFINXZDINX-NEXT: neg a5, a1
613-
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
614-
; RV32IZFINXZDINX-NEXT: neg a2, a2
615-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
616-
; RV32IZFINXZDINX-NEXT: neg a2, a4
617-
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
618-
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
615+
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
619616
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
620617
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
621618
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -837,30 +834,29 @@ define i64 @test_round_si64(double %x) nounwind {
837834
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI13_0)
838835
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI13_0+4)(a2)
839836
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI13_0)(a2)
840-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
837+
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI13_1)
838+
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI13_1+4)(a4)
839+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI13_1)(a4)
840+
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
841+
; RV32IZFINXZDINX-NEXT: neg a2, a6
842+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
843+
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
844+
; RV32IZFINXZDINX-NEXT: neg a2, a4
845+
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
846+
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
847+
; RV32IZFINXZDINX-NEXT: neg a2, a2
841848
; RV32IZFINXZDINX-NEXT: lui a5, 524288
842-
; RV32IZFINXZDINX-NEXT: li a4, 1
843849
; RV32IZFINXZDINX-NEXT: lui a3, 524288
844-
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB13_2
850+
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB13_2
845851
; RV32IZFINXZDINX-NEXT: # %bb.1:
846852
; RV32IZFINXZDINX-NEXT: mv a3, a1
847853
; RV32IZFINXZDINX-NEXT: .LBB13_2:
848-
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI13_1)
849-
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI13_1)(a1)
850-
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI13_1+4)(a1)
851-
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
854+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
852855
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB13_4
853856
; RV32IZFINXZDINX-NEXT: # %bb.3:
854857
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
855858
; RV32IZFINXZDINX-NEXT: .LBB13_4:
856-
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
857-
; RV32IZFINXZDINX-NEXT: neg a5, a1
858-
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
859-
; RV32IZFINXZDINX-NEXT: neg a2, a2
860-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
861-
; RV32IZFINXZDINX-NEXT: neg a2, a4
862-
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
863-
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
859+
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
864860
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
865861
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
866862
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -1082,30 +1078,29 @@ define i64 @test_roundeven_si64(double %x) nounwind {
10821078
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI17_0)
10831079
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI17_0+4)(a2)
10841080
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI17_0)(a2)
1085-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
1081+
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI17_1)
1082+
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI17_1+4)(a4)
1083+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI17_1)(a4)
1084+
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
1085+
; RV32IZFINXZDINX-NEXT: neg a2, a6
1086+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
1087+
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
1088+
; RV32IZFINXZDINX-NEXT: neg a2, a4
1089+
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
1090+
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
1091+
; RV32IZFINXZDINX-NEXT: neg a2, a2
10861092
; RV32IZFINXZDINX-NEXT: lui a5, 524288
1087-
; RV32IZFINXZDINX-NEXT: li a4, 1
10881093
; RV32IZFINXZDINX-NEXT: lui a3, 524288
1089-
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB17_2
1094+
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB17_2
10901095
; RV32IZFINXZDINX-NEXT: # %bb.1:
10911096
; RV32IZFINXZDINX-NEXT: mv a3, a1
10921097
; RV32IZFINXZDINX-NEXT: .LBB17_2:
1093-
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI17_1)
1094-
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI17_1)(a1)
1095-
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI17_1+4)(a1)
1096-
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
1098+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
10971099
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB17_4
10981100
; RV32IZFINXZDINX-NEXT: # %bb.3:
10991101
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
11001102
; RV32IZFINXZDINX-NEXT: .LBB17_4:
1101-
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
1102-
; RV32IZFINXZDINX-NEXT: neg a5, a1
1103-
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
1104-
; RV32IZFINXZDINX-NEXT: neg a2, a2
1105-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
1106-
; RV32IZFINXZDINX-NEXT: neg a2, a4
1107-
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
1108-
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
1103+
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
11091104
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
11101105
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
11111106
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
@@ -1327,30 +1322,29 @@ define i64 @test_rint_si64(double %x) nounwind {
13271322
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI21_0)
13281323
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI21_0+4)(a2)
13291324
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI21_0)(a2)
1330-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
1325+
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI21_1)
1326+
; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI21_1+4)(a4)
1327+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI21_1)(a4)
1328+
; RV32IZFINXZDINX-NEXT: fle.d a6, a2, s0
1329+
; RV32IZFINXZDINX-NEXT: neg a2, a6
1330+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
1331+
; RV32IZFINXZDINX-NEXT: flt.d a4, a4, s0
1332+
; RV32IZFINXZDINX-NEXT: neg a2, a4
1333+
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
1334+
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
1335+
; RV32IZFINXZDINX-NEXT: neg a2, a2
13311336
; RV32IZFINXZDINX-NEXT: lui a5, 524288
1332-
; RV32IZFINXZDINX-NEXT: li a4, 1
13331337
; RV32IZFINXZDINX-NEXT: lui a3, 524288
1334-
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB21_2
1338+
; RV32IZFINXZDINX-NEXT: beqz a6, .LBB21_2
13351339
; RV32IZFINXZDINX-NEXT: # %bb.1:
13361340
; RV32IZFINXZDINX-NEXT: mv a3, a1
13371341
; RV32IZFINXZDINX-NEXT: .LBB21_2:
1338-
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI21_1)
1339-
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI21_1)(a1)
1340-
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI21_1+4)(a1)
1341-
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
1342+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
13421343
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB21_4
13431344
; RV32IZFINXZDINX-NEXT: # %bb.3:
13441345
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
13451346
; RV32IZFINXZDINX-NEXT: .LBB21_4:
1346-
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
1347-
; RV32IZFINXZDINX-NEXT: neg a5, a1
1348-
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
1349-
; RV32IZFINXZDINX-NEXT: neg a2, a2
1350-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
1351-
; RV32IZFINXZDINX-NEXT: neg a2, a4
1352-
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
1353-
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
1347+
; RV32IZFINXZDINX-NEXT: and a1, a2, a3
13541348
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
13551349
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
13561350
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload

0 commit comments

Comments
 (0)