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[RISCV] Use Zvhmin instead of Zvfh on RUN lines for some intrinsic tests. NFC (#101540)
Loads/stores/reinterpret/vfncvt.f.f.w/vfwcvt.f.f.v/vmerge/vmv.v.v are all expected to work for f16 vectors with Zvfhmin. Remove the handcrafted Zvfhmin test that partially tested this. Splits the vfwcvt.f.f.v and vfncvt.f.f.w tests into their own file so we can have a separate RUN line from the float<->int conversions.
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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c

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‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c

Lines changed: 0 additions & 180 deletions
Original file line numberDiff line numberDiff line change
@@ -327,56 +327,6 @@ vfloat32m8_t test_vfwcvt_f_xu_v_f32m8(vuint16m4_t src, size_t vl) {
327327
return __riscv_vfwcvt_f_xu_v_f32m8(src, vl);
328328
}
329329

330-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2
331-
// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
332-
// CHECK-RV64-NEXT: entry:
333-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> [[SRC]], i64 [[VL]])
334-
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
335-
//
336-
vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
337-
return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
338-
}
339-
340-
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1
341-
// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
342-
// CHECK-RV64-NEXT: entry:
343-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[SRC]], i64 [[VL]])
344-
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
345-
//
346-
vfloat32m1_t test_vfwcvt_f_f_v_f32m1(vfloat16mf2_t src, size_t vl) {
347-
return __riscv_vfwcvt_f_f_v_f32m1(src, vl);
348-
}
349-
350-
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2
351-
// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
352-
// CHECK-RV64-NEXT: entry:
353-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> [[SRC]], i64 [[VL]])
354-
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
355-
//
356-
vfloat32m2_t test_vfwcvt_f_f_v_f32m2(vfloat16m1_t src, size_t vl) {
357-
return __riscv_vfwcvt_f_f_v_f32m2(src, vl);
358-
}
359-
360-
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4
361-
// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
362-
// CHECK-RV64-NEXT: entry:
363-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> [[SRC]], i64 [[VL]])
364-
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
365-
//
366-
vfloat32m4_t test_vfwcvt_f_f_v_f32m4(vfloat16m2_t src, size_t vl) {
367-
return __riscv_vfwcvt_f_f_v_f32m4(src, vl);
368-
}
369-
370-
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8
371-
// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
372-
// CHECK-RV64-NEXT: entry:
373-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> [[SRC]], i64 [[VL]])
374-
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
375-
//
376-
vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
377-
return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
378-
}
379-
380330
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1
381331
// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
382332
// CHECK-RV64-NEXT: entry:
@@ -537,46 +487,6 @@ vfloat64m8_t test_vfwcvt_f_xu_v_f64m8(vuint32m4_t src, size_t vl) {
537487
return __riscv_vfwcvt_f_xu_v_f64m8(src, vl);
538488
}
539489

540-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1
541-
// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
542-
// CHECK-RV64-NEXT: entry:
543-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[SRC]], i64 [[VL]])
544-
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
545-
//
546-
vfloat64m1_t test_vfwcvt_f_f_v_f64m1(vfloat32mf2_t src, size_t vl) {
547-
return __riscv_vfwcvt_f_f_v_f64m1(src, vl);
548-
}
549-
550-
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2
551-
// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
552-
// CHECK-RV64-NEXT: entry:
553-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> [[SRC]], i64 [[VL]])
554-
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
555-
//
556-
vfloat64m2_t test_vfwcvt_f_f_v_f64m2(vfloat32m1_t src, size_t vl) {
557-
return __riscv_vfwcvt_f_f_v_f64m2(src, vl);
558-
}
559-
560-
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4
561-
// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
562-
// CHECK-RV64-NEXT: entry:
563-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> [[SRC]], i64 [[VL]])
564-
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
565-
//
566-
vfloat64m4_t test_vfwcvt_f_f_v_f64m4(vfloat32m2_t src, size_t vl) {
567-
return __riscv_vfwcvt_f_f_v_f64m4(src, vl);
568-
}
569-
570-
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8
571-
// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
572-
// CHECK-RV64-NEXT: entry:
573-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> [[SRC]], i64 [[VL]])
574-
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
575-
//
576-
vfloat64m8_t test_vfwcvt_f_f_v_f64m8(vfloat32m4_t src, size_t vl) {
577-
return __riscv_vfwcvt_f_f_v_f64m8(src, vl);
578-
}
579-
580490
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfwcvt_f_x_v_f16mf4_m
581491
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
582492
// CHECK-RV64-NEXT: entry:
@@ -897,56 +807,6 @@ vfloat32m8_t test_vfwcvt_f_xu_v_f32m8_m(vbool4_t mask, vuint16m4_t src, size_t v
897807
return __riscv_vfwcvt_f_xu_v_f32m8_m(mask, src, vl);
898808
}
899809

900-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfwcvt_f_f_v_f32mf2_m
901-
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
902-
// CHECK-RV64-NEXT: entry:
903-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(<vscale x 1 x float> poison, <vscale x 1 x half> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
904-
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
905-
//
906-
vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2_m(vbool64_t mask, vfloat16mf4_t src, size_t vl) {
907-
return __riscv_vfwcvt_f_f_v_f32mf2_m(mask, src, vl);
908-
}
909-
910-
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfwcvt_f_f_v_f32m1_m
911-
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
912-
// CHECK-RV64-NEXT: entry:
913-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> poison, <vscale x 2 x half> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
914-
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
915-
//
916-
vfloat32m1_t test_vfwcvt_f_f_v_f32m1_m(vbool32_t mask, vfloat16mf2_t src, size_t vl) {
917-
return __riscv_vfwcvt_f_f_v_f32m1_m(mask, src, vl);
918-
}
919-
920-
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfwcvt_f_f_v_f32m2_m
921-
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
922-
// CHECK-RV64-NEXT: entry:
923-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
924-
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
925-
//
926-
vfloat32m2_t test_vfwcvt_f_f_v_f32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) {
927-
return __riscv_vfwcvt_f_f_v_f32m2_m(mask, src, vl);
928-
}
929-
930-
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfwcvt_f_f_v_f32m4_m
931-
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
932-
// CHECK-RV64-NEXT: entry:
933-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16.i64(<vscale x 8 x float> poison, <vscale x 8 x half> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
934-
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
935-
//
936-
vfloat32m4_t test_vfwcvt_f_f_v_f32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) {
937-
return __riscv_vfwcvt_f_f_v_f32m4_m(mask, src, vl);
938-
}
939-
940-
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfwcvt_f_f_v_f32m8_m
941-
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
942-
// CHECK-RV64-NEXT: entry:
943-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16.i64(<vscale x 16 x float> poison, <vscale x 16 x half> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3)
944-
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
945-
//
946-
vfloat32m8_t test_vfwcvt_f_f_v_f32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) {
947-
return __riscv_vfwcvt_f_f_v_f32m8_m(mask, src, vl);
948-
}
949-
950810
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vfwcvt_x_f_v_i64m1_m
951811
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
952812
// CHECK-RV64-NEXT: entry:
@@ -1107,46 +967,6 @@ vfloat64m8_t test_vfwcvt_f_xu_v_f64m8_m(vbool8_t mask, vuint32m4_t src, size_t v
1107967
return __riscv_vfwcvt_f_xu_v_f64m8_m(mask, src, vl);
1108968
}
1109969

1110-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfwcvt_f_f_v_f64m1_m
1111-
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1112-
// CHECK-RV64-NEXT: entry:
1113-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
1114-
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
1115-
//
1116-
vfloat64m1_t test_vfwcvt_f_f_v_f64m1_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
1117-
return __riscv_vfwcvt_f_f_v_f64m1_m(mask, src, vl);
1118-
}
1119-
1120-
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfwcvt_f_f_v_f64m2_m
1121-
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1122-
// CHECK-RV64-NEXT: entry:
1123-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32.i64(<vscale x 2 x double> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
1124-
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
1125-
//
1126-
vfloat64m2_t test_vfwcvt_f_f_v_f64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
1127-
return __riscv_vfwcvt_f_f_v_f64m2_m(mask, src, vl);
1128-
}
1129-
1130-
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfwcvt_f_f_v_f64m4_m
1131-
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1132-
// CHECK-RV64-NEXT: entry:
1133-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32.i64(<vscale x 4 x double> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3)
1134-
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
1135-
//
1136-
vfloat64m4_t test_vfwcvt_f_f_v_f64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
1137-
return __riscv_vfwcvt_f_f_v_f64m4_m(mask, src, vl);
1138-
}
1139-
1140-
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfwcvt_f_f_v_f64m8_m
1141-
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1142-
// CHECK-RV64-NEXT: entry:
1143-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32.i64(<vscale x 8 x double> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3)
1144-
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
1145-
//
1146-
vfloat64m8_t test_vfwcvt_f_f_v_f64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
1147-
return __riscv_vfwcvt_f_f_v_f64m8_m(mask, src, vl);
1148-
}
1149-
1150970
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfwcvt_x_f_v_i32mf2_rm
1151971
// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1152972
// CHECK-RV64-NEXT: entry:

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