[RISCV] Use Zvhmin instead of Zvfh on RUN lines for some intrinsic tests. NFC #101540
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…sts. Loads/stores/reinterpret/vfncvt.f.f.w/vfwcvt.f.f.v/vmerge/vmv.v.v are all expected to work for f16 vectors with Zvfhmin. Remove the handcrafted Zvfhmin test that partially tested this. Splits the vfwcvt.f.f.v and vfncvt.f.f.w tests into their own file so we can have a separate RUN line from the float<->int conversions.
topperc
requested review from
rofirrim,
lukel97,
kito-cheng,
jacquesguan,
4vtomat and
wangpc-pp
topperc
changed the title
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@llvm/pr-subscribers-clang Author: Craig Topper (topperc) ChangesLoads/stores/reinterpret/vfncvt.f.f.w/vfwcvt.f.f.v/vmerge/vmv.v.v are all expected to work for f16 vectors with Zvfhmin. Remove the handcrafted Zvfhmin test that partially tested this. Splits the vfwcvt.f.f.v and vfncvt.f.f.w tests into their own file so we can have a separate RUN line from the float<->int conversions. Patch is 954.36 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/101540.diff 544 Files Affected:
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
index dcdfb7be46ad6..ba164258552fe 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
@@ -327,55 +327,6 @@ vfloat16m4_t test_vfncvt_f_xu_w_f16m4(vuint32m8_t src, size_t vl) {
return __riscv_vfncvt_f_xu_w_f16m4(src, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4
-// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2
-// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vfncvt_f_f_w_f16mf2(vfloat32m1_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16mf2(src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1
-// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m1(src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2
-// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vfncvt_f_f_w_f16m2(vfloat32m4_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m2(src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4
-// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m4(src, vl);
-}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2
// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
@@ -537,46 +488,6 @@ vfloat32m4_t test_vfncvt_f_xu_w_f32m4(vuint64m8_t src, size_t vl) {
return __riscv_vfncvt_f_xu_w_f32m4(src, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2
-// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vfncvt_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32mf2(src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1
-// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vfncvt_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m1(src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2
-// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vfncvt_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m2(src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4
-// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> [[SRC]], i64 7, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vfncvt_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m4(src, vl);
-}
-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
@@ -897,56 +808,6 @@ vfloat16m4_t test_vfncvt_f_xu_w_f16m4_m(vbool4_t mask, vuint32m8_t src, size_t v
return __riscv_vfncvt_f_xu_w_f16m4_m(mask, src, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vfncvt_f_f_w_f16mf4_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16mf4_m(mask, src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vfncvt_f_f_w_f16mf2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16mf2_m(mask, src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vfncvt_f_f_w_f16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m1_m(mask, src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vfncvt_f_f_w_f16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m2_m(mask, src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> [[SRC]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vfncvt_f_f_w_f16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m4_m(mask, src, vl);
-}
-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
@@ -1107,46 +968,6 @@ vfloat32m4_t test_vfncvt_f_xu_w_f32m4_m(vbool8_t mask, vuint64m8_t src, size_t v
return __riscv_vfncvt_f_xu_w_f32m4_m(mask, src, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vfncvt_f_f_w_f32mf2_m(vbool64_t mask, vfloat64m1_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32mf2_m(mask, src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> [[SRC]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vfncvt_f_f_w_f32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m1_m(mask, src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> [[SRC]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vfncvt_f_f_w_f32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m2_m(mask, src, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> [[SRC]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vfncvt_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m4_m(mask, src, vl);
-}
-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
@@ -1467,56 +1288,6 @@ vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm(vuint32m8_t src, size_t vl) {
return __riscv_vfncvt_f_xu_w_f16m4_rm(src, __RISCV_FRM_RNE, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_rm
-// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vfncvt_f_f_w_f16mf4_rm(vfloat32mf2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16mf4_rm(src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_rm
-// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> poison, <vscale x 2 x float> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vfncvt_f_f_w_f16mf2_rm(vfloat32m1_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16mf2_rm(src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfncvt_f_f_w_f16m1_rm
-// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vfncvt_f_f_w_f16m1_rm(vfloat32m2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m1_rm(src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfncvt_f_f_w_f16m2_rm
-// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> poison, <vscale x 8 x float> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vfncvt_f_f_w_f16m2_rm(vfloat32m4_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m2_rm(src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfncvt_f_f_w_f16m4_rm
-// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> poison, <vscale x 16 x float> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vfncvt_f_f_w_f16m4_rm(vfloat32m8_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16m4_rm(src, __RISCV_FRM_RNE, vl);
-}
-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vfncvt_x_f_w_i32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
@@ -1677,46 +1448,6 @@ vfloat32m4_t test_vfncvt_f_xu_w_f32m4_rm(vuint64m8_t src, size_t vl) {
return __riscv_vfncvt_f_xu_w_f32m4_rm(src, __RISCV_FRM_RNE, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfncvt_f_f_w_f32mf2_rm
-// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> poison, <vscale x 1 x double> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vfncvt_f_f_w_f32mf2_rm(vfloat64m1_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32mf2_rm(src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfncvt_f_f_w_f32m1_rm
-// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> poison, <vscale x 2 x double> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vfncvt_f_f_w_f32m1_rm(vfloat64m2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m1_rm(src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfncvt_f_f_w_f32m2_rm
-// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> poison, <vscale x 4 x double> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vfncvt_f_f_w_f32m2_rm(vfloat64m4_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m2_rm(src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfncvt_f_f_w_f32m4_rm
-// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> poison, <vscale x 8 x double> [[SRC]], i64 0, i64 [[VL]])
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vfncvt_f_f_w_f32m4_rm(vfloat64m8_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f32m4_rm(src, __RISCV_FRM_RNE, vl);
-}
-
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_x_f_w_i8mf8_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
@@ -2037,56 +1768,6 @@ vfloat16m4_t test_vfncvt_f_xu_w_f16m4_rm_m(vbool4_t mask, vuint32m8_t src, size_
return __riscv_vfncvt_f_xu_w_f16m4_rm_m(mask, src, __RISCV_FRM_RNE, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfncvt_f_f_w_f16mf4_rm_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(<vscale x 1 x half> poison, <vscale x 1 x float> [[SRC]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vfncvt_f_f_w_f16mf4_rm_m(vbool64_t mask, vfloat32mf2_t src, size_t vl) {
- return __riscv_vfncvt_f_f_w_f16mf4_rm_m(mask, src, __RISCV_FRM_RNE, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfncvt_f_f_w_f16mf2_rm_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]]...
[truncated]
|
|
Do we want vget/vset/vcreate/vundefined use |
topperc
changed the title
Yes, according to the feedback on riscv-non-isa/rvv-intrinsic-doc#351. I believe that requires a change to riscv_vector.td so it's out of scope for this patch. |
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Loads/stores/reinterpret/vfncvt.f.f.w/vfwcvt.f.f.v/vmerge/vmv.v.v are all expected to work for f16 vectors with Zvfhmin.
Remove the handcrafted Zvfhmin test that partially tested this.
Splits the vfwcvt.f.f.v and vfncvt.f.f.w tests into their own file so we can have a separate RUN line from the float<->int conversions.