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[mlir][ArmSME] Provide descriptions and summaries for intrinsic types (#71057)
Follow on for some types missed in #70920. This also replaces the LDSTPredicate with SVEPredicate (as they are equivalent), and adds a missing rank == 1 checks to the SVE vector types. A FIXME is also added to point out an issue in the MOPVector type constraint.
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mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td

Lines changed: 36 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,40 @@ include "ArmSME.td"
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// ArmSME Intrinsic op definitions
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//===----------------------------------------------------------------------===//
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def MOPPredicate : ScalableVectorOfLengthAndType<[16, 8, 4, 2], [I1]>;
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def MOPVector : ScalableVectorOfLengthAndType<[16, 8, 4, 2],
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[I8, I16, BF16, F16, F32, F64]>;
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def LDSTPredicate : ScalableVectorOfLengthAndType<[16, 8, 4, 2, 1], [I1]>;
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def MOPPredicate : ScalableVectorOfRankAndLengthAndType<[1], [16, 8, 4, 2], [I1]>
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{
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let summary = "a vector type that is a supported predicate for the SME MOP instructions";
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let description = [{
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Possible vector types:
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* `vector<[16]xi1>`
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* `vector<[8]xi1>`
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* `vector<[4]xi1>`
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* `vector<[2]xi1>`
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}];
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}
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// FIXME: This allows types that are not SVE vectors, e.g. vector<[16]xf32>.
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def MOPVector : ScalableVectorOfRankAndLengthAndType<[1], [16, 8, 4, 2],
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[I8, I16, BF16, F16, F32, F64]>
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{
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let summary = "a vector type that is a supported input for the SME MOP instructions";
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let description = [{
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Possible vector types:
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Integer elements:
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* `vector<[16]xi8>`
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* `vector<[8]xi16>`
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Floating point elements:
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* `vector<[8]xf16>`
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* `vector<[8]xbf16>`
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* `vector<[4]xf32>`
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* `vector<[2]xf64>`
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}];
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}
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class ArmSME_IntrOp<string mnemonic, list<int> overloadedOperands = [],
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list<Trait> traits = [], int numResults = 0,
@@ -65,7 +95,7 @@ def LLVM_aarch64_sme_usmops_wide : ArmSME_IntrMopOverloadedOp<"usmops.wide">;
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// Loads
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class ArmSME_IntrLoadOp<string mnemonic>
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: ArmSME_IntrOp<mnemonic>,
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Arguments<(ins Arg<LDSTPredicate, "Vector predicate">:$predicate,
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Arguments<(ins Arg<SVEPredicate, "Vector predicate">:$predicate,
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Arg<LLVM_AnyPointer, "Load address">:$load_address,
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Arg<I32, "Virtual tile ID">:$tile_id,
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Arg<I32, "Tile slice">:$tile_slice_index)>;
@@ -84,7 +114,7 @@ def LLVM_aarch64_sme_ld1q_vert : ArmSME_IntrLoadOp<"ld1q.vert">;
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// Stores
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class ArmSME_IntrStoreOp<string mnemonic>
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: ArmSME_IntrOp<mnemonic>,
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Arguments<(ins Arg<LDSTPredicate, "Vector predicate">:$predicate,
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Arguments<(ins Arg<SVEPredicate, "Vector predicate">:$predicate,
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Arg<LLVM_AnyPointer, "Store address", [MemWrite]>:$store_address,
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Arg<I32, "Virtual tile ID">:$tile_id,
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Arg<I32, "Tile slice">:$tile_slice_index)>;

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