[mlir][ArmSME] Provide descriptions and summaries for intrinsic types #71057
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Follow on for some types missed in llvm#70920. This also replaces the LDSTPredicate with SVEPredicate (as they are equivalent), and adds a missing rank == 1 checks to the SVE vector types. A FIXME is also added to point out an issue in the MOPVector type constraint.
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@llvm/pr-subscribers-mlir Author: Benjamin Maxwell (MacDue) ChangesFollow on for some types missed in #70920. This also replaces the LDSTPredicate with SVEPredicate (as they are equivalent), and adds a missing rank == 1 checks to the SVE vector types. A FIXME is also added to point out an issue in the MOPVector type constraint. Full diff: https://github.com/llvm/llvm-project/pull/71057.diff 1 Files Affected:
diff --git a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
index e369ef203ad39d6..c86a73812a5899c 100644
--- a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
+++ b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
@@ -19,10 +19,40 @@ include "ArmSME.td"
// ArmSME Intrinsic op definitions
//===----------------------------------------------------------------------===//
-def MOPPredicate : ScalableVectorOfLengthAndType<[16, 8, 4, 2], [I1]>;
-def MOPVector : ScalableVectorOfLengthAndType<[16, 8, 4, 2],
- [I8, I16, BF16, F16, F32, F64]>;
-def LDSTPredicate : ScalableVectorOfLengthAndType<[16, 8, 4, 2, 1], [I1]>;
+def MOPPredicate : ScalableVectorOfRankAndLengthAndType<[1], [16, 8, 4, 2], [I1]>
+{
+ let summary = "a vector type that is a supported predicate for the SME MOP instructions";
+ let description = [{
+ Possible vector types:
+
+ * `vector<[16]xi1>`
+ * `vector<[8]xi1>`
+ * `vector<[4]xi1>`
+ * `vector<[2]xi1>`
+ }];
+}
+
+// FIXME: This allows types that are not SVE vectors, e.g. vector<[16]xf32>.
+def MOPVector : ScalableVectorOfRankAndLengthAndType<[1], [16, 8, 4, 2],
+ [I8, I16, BF16, F16, F32, F64]>
+{
+ let summary = "a vector type that is a supported input for the SME MOP instructions";
+ let description = [{
+ Possible vector types:
+
+ Integer elements:
+
+ * `vector<[16]xi8>`
+ * `vector<[8]xi16>`
+
+ Floating point elements:
+
+ * `vector<[8]xf16>`
+ * `vector<[8]xbf16>`
+ * `vector<[4]xf32>`
+ * `vector<[2]xf64>`
+ }];
+}
class ArmSME_IntrOp<string mnemonic, list<int> overloadedOperands = [],
list<Trait> traits = [], int numResults = 0,
@@ -65,7 +95,7 @@ def LLVM_aarch64_sme_usmops_wide : ArmSME_IntrMopOverloadedOp<"usmops.wide">;
// Loads
class ArmSME_IntrLoadOp<string mnemonic>
: ArmSME_IntrOp<mnemonic>,
- Arguments<(ins Arg<LDSTPredicate, "Vector predicate">:$predicate,
+ Arguments<(ins Arg<SVEPredicate, "Vector predicate">:$predicate,
Arg<LLVM_AnyPointer, "Load address">:$load_address,
Arg<I32, "Virtual tile ID">:$tile_id,
Arg<I32, "Tile slice">:$tile_slice_index)>;
@@ -84,7 +114,7 @@ def LLVM_aarch64_sme_ld1q_vert : ArmSME_IntrLoadOp<"ld1q.vert">;
// Stores
class ArmSME_IntrStoreOp<string mnemonic>
: ArmSME_IntrOp<mnemonic>,
- Arguments<(ins Arg<LDSTPredicate, "Vector predicate">:$predicate,
+ Arguments<(ins Arg<SVEPredicate, "Vector predicate">:$predicate,
Arg<LLVM_AnyPointer, "Store address", [MemWrite]>:$store_address,
Arg<I32, "Virtual tile ID">:$tile_id,
Arg<I32, "Tile slice">:$tile_slice_index)>;
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@llvm/pr-subscribers-mlir-sme Author: Benjamin Maxwell (MacDue) ChangesFollow on for some types missed in #70920. This also replaces the LDSTPredicate with SVEPredicate (as they are equivalent), and adds a missing rank == 1 checks to the SVE vector types. A FIXME is also added to point out an issue in the MOPVector type constraint. Full diff: https://github.com/llvm/llvm-project/pull/71057.diff 1 Files Affected:
diff --git a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
index e369ef203ad39d6..c86a73812a5899c 100644
--- a/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
+++ b/mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEIntrinsicOps.td
@@ -19,10 +19,40 @@ include "ArmSME.td"
// ArmSME Intrinsic op definitions
//===----------------------------------------------------------------------===//
-def MOPPredicate : ScalableVectorOfLengthAndType<[16, 8, 4, 2], [I1]>;
-def MOPVector : ScalableVectorOfLengthAndType<[16, 8, 4, 2],
- [I8, I16, BF16, F16, F32, F64]>;
-def LDSTPredicate : ScalableVectorOfLengthAndType<[16, 8, 4, 2, 1], [I1]>;
+def MOPPredicate : ScalableVectorOfRankAndLengthAndType<[1], [16, 8, 4, 2], [I1]>
+{
+ let summary = "a vector type that is a supported predicate for the SME MOP instructions";
+ let description = [{
+ Possible vector types:
+
+ * `vector<[16]xi1>`
+ * `vector<[8]xi1>`
+ * `vector<[4]xi1>`
+ * `vector<[2]xi1>`
+ }];
+}
+
+// FIXME: This allows types that are not SVE vectors, e.g. vector<[16]xf32>.
+def MOPVector : ScalableVectorOfRankAndLengthAndType<[1], [16, 8, 4, 2],
+ [I8, I16, BF16, F16, F32, F64]>
+{
+ let summary = "a vector type that is a supported input for the SME MOP instructions";
+ let description = [{
+ Possible vector types:
+
+ Integer elements:
+
+ * `vector<[16]xi8>`
+ * `vector<[8]xi16>`
+
+ Floating point elements:
+
+ * `vector<[8]xf16>`
+ * `vector<[8]xbf16>`
+ * `vector<[4]xf32>`
+ * `vector<[2]xf64>`
+ }];
+}
class ArmSME_IntrOp<string mnemonic, list<int> overloadedOperands = [],
list<Trait> traits = [], int numResults = 0,
@@ -65,7 +95,7 @@ def LLVM_aarch64_sme_usmops_wide : ArmSME_IntrMopOverloadedOp<"usmops.wide">;
// Loads
class ArmSME_IntrLoadOp<string mnemonic>
: ArmSME_IntrOp<mnemonic>,
- Arguments<(ins Arg<LDSTPredicate, "Vector predicate">:$predicate,
+ Arguments<(ins Arg<SVEPredicate, "Vector predicate">:$predicate,
Arg<LLVM_AnyPointer, "Load address">:$load_address,
Arg<I32, "Virtual tile ID">:$tile_id,
Arg<I32, "Tile slice">:$tile_slice_index)>;
@@ -84,7 +114,7 @@ def LLVM_aarch64_sme_ld1q_vert : ArmSME_IntrLoadOp<"ld1q.vert">;
// Stores
class ArmSME_IntrStoreOp<string mnemonic>
: ArmSME_IntrOp<mnemonic>,
- Arguments<(ins Arg<LDSTPredicate, "Vector predicate">:$predicate,
+ Arguments<(ins Arg<SVEPredicate, "Vector predicate">:$predicate,
Arg<LLVM_AnyPointer, "Store address", [MemWrite]>:$store_address,
Arg<I32, "Virtual tile ID">:$tile_id,
Arg<I32, "Tile slice">:$tile_slice_index)>;
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Follow on for some types missed in #70920. This also replaces the LDSTPredicate with SVEPredicate (as they are equivalent), and adds a missing rank == 1 checks to the SVE vector types.
A FIXME is also added to point out an issue in the MOPVector type constraint.