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[TableGen] Add a backend to generate MacroFusion predicators (#72222)
`FusionPredicate` is used to predicate if target instruction matches the requirement. The targets can be firstMI, secondMI or both. The `Fusion` contains a list of `FusionPredicate`. The generated code will be like: ``` bool isNAME(const TargetInstrInfo &TII, const TargetSubtargetInfo &STI, const MachineInstr *FirstMI, const MachineInstr &SecondMI) { auto &MRI = SecondMI.getMF()->getRegInfo(); /* Predicates */ return true; } ``` A boilerplate class called `SimpleFusion` is added. `SimpleFusion` has a predefined structure of predicates and accepts predicate for `firstMI`, predicate for `secondMI` and epilog/prolog as arguments. The generated code for `SimpleFusion` will be like: ``` bool isNAME(const TargetInstrInfo &TII, const TargetSubtargetInfo &STI, const MachineInstr *FirstMI, const MachineInstr &SecondMI) { auto &MRI = SecondMI.getMF()->getRegInfo(); /* Prolog */ /* Predicate for `SecondMI` */ /* Wildcard */ /* Predicate for `FirstMI` */ /* Check One Use */ /* Tie registers */ /* Epilog */ return true; } ```
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‎llvm/include/llvm/Target/TargetInstrPredicate.td

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@@ -95,6 +95,12 @@ class MCOperandPredicate<int Index> : MCInstPredicate {
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// Return true if machine operand at position `Index` is a register operand.
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class CheckIsRegOperand<int Index> : MCOperandPredicate<Index>;
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// Return true if machine operand at position `Index` is a virtual register operand.
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class CheckIsVRegOperand<int Index> : MCOperandPredicate<Index>;
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// Return true if machine operand at position `Index` is not a virtual register operand.
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class CheckIsNotVRegOperand<int Index> : CheckNot<CheckIsVRegOperand<Index>>;
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// Return true if machine operand at position `Index` is an immediate operand.
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class CheckIsImmOperand<int Index> : MCOperandPredicate<Index>;
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‎llvm/include/llvm/Target/TargetSchedule.td

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@@ -584,3 +584,116 @@ class MemoryQueue<ProcResourceKind PR> {
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class LoadQueue<ProcResourceKind LDQueue> : MemoryQueue<LDQueue>;
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class StoreQueue<ProcResourceKind STQueue> : MemoryQueue<STQueue>;
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// The target instruction that FusionPredicate will be evaluated on.
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class FusionTarget;
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def first_fusion_target : FusionTarget;
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def second_fusion_target : FusionTarget;
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def both_fusion_target : FusionTarget;
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// Base class of FusionPredicate, etc. The avaliable variables are:
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// * const TargetInstrInfo &TII
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// * const TargetSubtargetInfo &STI
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// * const MachineRegisterInfo &MRI
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// * const MachineInstr *FirstMI
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// * const MachineInstr &SecondMI
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class FusionPredicate<FusionTarget target> {
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FusionTarget Target = target;
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}
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class FirstFusionPredicate: FusionPredicate<first_fusion_target>;
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class SecondFusionPredicate: FusionPredicate<second_fusion_target>;
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class BothFusionPredicate: FusionPredicate<both_fusion_target>;
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// FusionPredicate with raw code predicate.
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class FusionPredicateWithCode<code pred> : FusionPredicate<both_fusion_target> {
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code Predicate = pred;
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}
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// FusionPredicate with MCInstPredicate.
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class FusionPredicateWithMCInstPredicate<FusionTarget target, MCInstPredicate pred>
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: FusionPredicate<target> {
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MCInstPredicate Predicate = pred;
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}
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class FirstFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
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: FusionPredicateWithMCInstPredicate<first_fusion_target, pred>;
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class SecondFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
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: FusionPredicateWithMCInstPredicate<second_fusion_target, pred>;
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// The pred will be applied on both firstMI and secondMI.
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class BothFusionPredicateWithMCInstPredicate<MCInstPredicate pred>
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: FusionPredicateWithMCInstPredicate<second_fusion_target, pred>;
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// Tie firstOpIdx and secondOpIdx. The operand of `FirstMI` at position
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// `firstOpIdx` should be the same as the operand of `SecondMI` at position
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// `secondOpIdx`.
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class TieReg<int firstOpIdx, int secondOpIdx> : BothFusionPredicate {
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int FirstOpIdx = firstOpIdx;
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int SecondOpIdx = secondOpIdx;
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}
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// A predicate for wildcard. The generated code will be like:
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// ```
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// if (!FirstMI)
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// return ReturnValue;
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// ```
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class WildcardPred<bit ret> : FirstFusionPredicate {
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bit ReturnValue = ret;
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}
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def WildcardFalse : WildcardPred<0>;
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def WildcardTrue : WildcardPred<1>;
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// Indicates that the destination register of `FirstMI` should have one use if
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// it is a virtual register.
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class OneUsePred : FirstFusionPredicate;
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def OneUse : OneUsePred;
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// Handled by MacroFusionPredicatorEmitter backend.
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// The generated predicator will be like:
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// ```
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// bool isNAME(const TargetInstrInfo &TII,
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// const TargetSubtargetInfo &STI,
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// const MachineInstr *FirstMI,
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// const MachineInstr &SecondMI) {
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// auto &MRI = SecondMI.getMF()->getRegInfo();
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// /* Predicates */
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// return true;
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// }
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// ```
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class Fusion<list<FusionPredicate> predicates> {
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list<FusionPredicate> Predicates = predicates;
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}
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// The generated predicator will be like:
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// ```
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// bool isNAME(const TargetInstrInfo &TII,
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// const TargetSubtargetInfo &STI,
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// const MachineInstr *FirstMI,
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// const MachineInstr &SecondMI) {
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// auto &MRI = SecondMI.getMF()->getRegInfo();
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// /* Prolog */
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// /* Predicate for `SecondMI` */
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// /* Wildcard */
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// /* Predicate for `FirstMI` */
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// /* Check One Use */
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// /* Tie registers */
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// /* Epilog */
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// return true;
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// }
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// ```
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class SimpleFusion<MCInstPredicate firstPred, MCInstPredicate secondPred,
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list<FusionPredicate> prolog = [],
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list<FusionPredicate> epilog = []>
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: Fusion<!listconcat(
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prolog,
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[
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SecondFusionPredicateWithMCInstPredicate<secondPred>,
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WildcardTrue,
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FirstFusionPredicateWithMCInstPredicate<firstPred>,
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SecondFusionPredicateWithMCInstPredicate<
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CheckAny<[
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CheckIsVRegOperand<0>,
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CheckSameRegOperand<0, 1>
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]>>,
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OneUse,
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TieReg<0, 1>,
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],
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epilog)>;

‎llvm/test/TableGen/MacroFusion.td

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// RUN: llvm-tblgen -gen-macro-fusion-pred -I %p/../../include %s | FileCheck %s --check-prefix=CHECK-PREDICATOR
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include "llvm/Target/Target.td"
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def TestInstrInfo : InstrInfo { }
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def TestAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def Test : Target {
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let InstructionSet = TestInstrInfo;
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let AssemblyWriters = [TestAsmWriter];
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}
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let Namespace = "Test" in {
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foreach i = 0-32 in {
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def X#i : Register<"x"#i>;
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}
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def GPR : RegisterClass<"GPR", [i32], 32, (sequence "X%u", 0, 32)>;
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class TestInst<int Opc> : Instruction {
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field bits<32> Inst;
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field bits<32> SoftFail = 0;
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let Size = 4;
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let Inst = Opc;
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let OutOperandList = (outs);
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let InOperandList = (ins);
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let AsmString = NAME;
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}
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}
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def Inst0 : TestInst<0>;
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def Inst1 : TestInst<1>;
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def TestFusion: SimpleFusion<CheckOpcode<[Inst0]>,
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CheckAll<[
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CheckOpcode<[Inst1]>,
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CheckRegOperand<0, X0>
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]>>;
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// CHECK-PREDICATOR: #ifdef GET_Test_MACRO_FUSION_PRED_DECL
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// CHECK-PREDICATOR-NEXT: #undef GET_Test_MACRO_FUSION_PRED_DECL
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// CHECK-PREDICATOR-EMPTY:
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// CHECK-PREDICATOR-NEXT: namespace llvm {
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// CHECK-PREDICATOR-NEXT: bool isTestFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &);
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// CHECK-PREDICATOR-NEXT: } // end namespace llvm
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// CHECK-PREDICATOR-EMPTY:
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// CHECK-PREDICATOR-NEXT: #endif
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// CHECK-PREDICATOR: #ifdef GET_Test_MACRO_FUSION_PRED_IMPL
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// CHECK-PREDICATOR-NEXT: #undef GET_Test_MACRO_FUSION_PRED_IMPL
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// CHECK-PREDICATOR-EMPTY:
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// CHECK-PREDICATOR-NEXT: namespace llvm {
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// CHECK-PREDICATOR-NEXT: bool isTestFusion(
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// CHECK-PREDICATOR-NEXT: const TargetInstrInfo &TII,
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// CHECK-PREDICATOR-NEXT: const TargetSubtargetInfo &STI,
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// CHECK-PREDICATOR-NEXT: const MachineInstr *FirstMI,
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// CHECK-PREDICATOR-NEXT: const MachineInstr &SecondMI) {
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// CHECK-PREDICATOR-NEXT: auto &MRI = SecondMI.getMF()->getRegInfo();
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// CHECK-PREDICATOR-NEXT: {
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// CHECK-PREDICATOR-NEXT: const MachineInstr *MI = &SecondMI;
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// CHECK-PREDICATOR-NEXT: if (!(
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// CHECK-PREDICATOR-NEXT: ( MI->getOpcode() == Test::Inst1 )
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// CHECK-PREDICATOR-NEXT: && MI->getOperand(0).getReg() == Test::X0
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// CHECK-PREDICATOR-NEXT: ))
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// CHECK-PREDICATOR-NEXT: return false;
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// CHECK-PREDICATOR-NEXT: }
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// CHECK-PREDICATOR-NEXT: if (!FirstMI)
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// CHECK-PREDICATOR-NEXT: return true;
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// CHECK-PREDICATOR-NEXT: {
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// CHECK-PREDICATOR-NEXT: const MachineInstr *MI = FirstMI;
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// CHECK-PREDICATOR-NEXT: if (( MI->getOpcode() != Test::Inst0 ))
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// CHECK-PREDICATOR-NEXT: return false;
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// CHECK-PREDICATOR-NEXT: }
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// CHECK-PREDICATOR-NEXT: {
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// CHECK-PREDICATOR-NEXT: const MachineInstr *MI = &SecondMI;
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// CHECK-PREDICATOR-NEXT: if (!(
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// CHECK-PREDICATOR-NEXT: MI->getOperand(0).getReg().isVirtual()
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// CHECK-PREDICATOR-NEXT: || MI->getOperand(0).getReg() == MI->getOperand(1).getReg()
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// CHECK-PREDICATOR-NEXT: ))
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// CHECK-PREDICATOR-NEXT: return false;
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// CHECK-PREDICATOR-NEXT: }
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// CHECK-PREDICATOR-NEXT: {
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// CHECK-PREDICATOR-NEXT: Register FirstDest = FirstMI->getOperand(0).getReg();
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// CHECK-PREDICATOR-NEXT: if (FirstDest.isVirtual() && !MRI.hasOneNonDBGUse(FirstDest))
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// CHECK-PREDICATOR-NEXT: return false;
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// CHECK-PREDICATOR-NEXT: }
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// CHECK-PREDICATOR-NEXT: if (!(FirstMI->getOperand(0).isReg() &&
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// CHECK-PREDICATOR-NEXT: SecondMI.getOperand(1).isReg() &&
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// CHECK-PREDICATOR-NEXT: FirstMI->getOperand(0).getReg() == SecondMI.getOperand(1).getReg()))
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// CHECK-PREDICATOR-NEXT: return false;
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// CHECK-PREDICATOR-NEXT: return true;
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// CHECK-PREDICATOR-NEXT: }
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// CHECK-PREDICATOR-NEXT: } // end namespace llvm
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// CHECK-PREDICATOR-EMPTY:
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// CHECK-PREDICATOR-NEXT: #endif

‎llvm/utils/TableGen/CMakeLists.txt

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@@ -72,6 +72,7 @@ add_tablegen(llvm-tblgen LLVM
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PredicateExpander.cpp
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PseudoLoweringEmitter.cpp
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CompressInstEmitter.cpp
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MacroFusionPredicatorEmitter.cpp
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RegisterBankEmitter.cpp
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RegisterInfoEmitter.cpp
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SearchableTableEmitter.cpp

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