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[llvm][RISCV] Support RISCV vector tuple type in llvm IR
Currently we have built-in C types for RISCV vector tuple type, e.g. `vint32m1x2_t`, however it's is represented as structure of scalable vector types, i.e. `{<vscale x 2 x i32>, <vscale x 2 x i32>}`. It loses the information for num_fields(NF) as struct is flattened during selection DAG, thus it makes it not possible to handle inline assembly of vector tuple type, it also makes the calling convention of vector tuple types handing not strait forward and hard to realize the allocation code, i.e. `RVVArgDispatcher`. This patch supports RISCV vector tuple types represented as `TargetExtType` which contains both `LMUL` and `NF`(num_fields) information and keep it all the way down to `selectionDAG` to match the corresponding `MVT`(support in the following patch). The llvm IR for the example above is then represented as `target("riscv_vec_tuple", <vscale x 8 x i8>, 2)` in which the first type parameter is the equivalent size scalable vecotr of i8 element type, the following integer parameter is the `NF` of the tuple. The new RISCV specific vector insert/extract intrinsics are also added as `llvm.riscv.vector.insert` and `llvm.riscv.vector.extract` to handle tuple type subvector inserttoin/extraction since the generic ones only operates on `VectorType` but not `TargetExtType`. There are total of 32 llvm types added for each `VREGS * NF <= 8`, where `VREGS` is the vector registers needed for each `LMUL` and `NF` is num_fields. The name of types are: ``` target("riscv_vec_tuple", <vscale x 1 x i8>, 2) // LMUL = mf8, NF = 2 target("riscv_vec_tuple", <vscale x 1 x i8>, 3) // LMUL = mf8, NF = 3 target("riscv_vec_tuple", <vscale x 1 x i8>, 4) // LMUL = mf8, NF = 4 target("riscv_vec_tuple", <vscale x 1 x i8>, 5) // LMUL = mf8, NF = 5 target("riscv_vec_tuple", <vscale x 1 x i8>, 6) // LMUL = mf8, NF = 6 target("riscv_vec_tuple", <vscale x 1 x i8>, 7) // LMUL = mf8, NF = 7 target("riscv_vec_tuple", <vscale x 1 x i8>, 8) // LMUL = mf8, NF = 8 target("riscv_vec_tuple", <vscale x 2 x i8>, 2) // LMUL = mf4, NF = 2 target("riscv_vec_tuple", <vscale x 2 x i8>, 3) // LMUL = mf4, NF = 3 target("riscv_vec_tuple", <vscale x 2 x i8>, 4) // LMUL = mf4, NF = 4 target("riscv_vec_tuple", <vscale x 2 x i8>, 5) // LMUL = mf4, NF = 5 target("riscv_vec_tuple", <vscale x 2 x i8>, 6) // LMUL = mf4, NF = 6 target("riscv_vec_tuple", <vscale x 2 x i8>, 7) // LMUL = mf4, NF = 7 target("riscv_vec_tuple", <vscale x 2 x i8>, 8) // LMUL = mf4, NF = 8 target("riscv_vec_tuple", <vscale x 4 x i8>, 2) // LMUL = mf2, NF = 2 target("riscv_vec_tuple", <vscale x 4 x i8>, 3) // LMUL = mf2, NF = 3 target("riscv_vec_tuple", <vscale x 4 x i8>, 4) // LMUL = mf2, NF = 4 target("riscv_vec_tuple", <vscale x 4 x i8>, 5) // LMUL = mf2, NF = 5 target("riscv_vec_tuple", <vscale x 4 x i8>, 6) // LMUL = mf2, NF = 6 target("riscv_vec_tuple", <vscale x 4 x i8>, 7) // LMUL = mf2, NF = 7 target("riscv_vec_tuple", <vscale x 4 x i8>, 8) // LMUL = mf2, NF = 8 target("riscv_vec_tuple", <vscale x 8 x i8>, 2) // LMUL = m1, NF = 2 target("riscv_vec_tuple", <vscale x 8 x i8>, 3) // LMUL = m1, NF = 3 target("riscv_vec_tuple", <vscale x 8 x i8>, 4) // LMUL = m1, NF = 4 target("riscv_vec_tuple", <vscale x 8 x i8>, 5) // LMUL = m1, NF = 5 target("riscv_vec_tuple", <vscale x 8 x i8>, 6) // LMUL = m1, NF = 6 target("riscv_vec_tuple", <vscale x 8 x i8>, 7) // LMUL = m1, NF = 7 target("riscv_vec_tuple", <vscale x 8 x i8>, 8) // LMUL = m1, NF = 8 target("riscv_vec_tuple", <vscale x 16 x i8>, 2) // LMUL = m2, NF = 2 target("riscv_vec_tuple", <vscale x 16 x i8>, 3) // LMUL = m2, NF = 3 target("riscv_vec_tuple", <vscale x 16 x i8>, 4) // LMUL = m2, NF = 4 target("riscv_vec_tuple", <vscale x 32 x i8>, 2) // LMUL = m4, NF = 2 ```
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clang/include/clang/Basic/riscv_vector.td

Lines changed: 107 additions & 90 deletions
Large diffs are not rendered by default.

clang/include/clang/Support/RISCVVIntrinsicUtils.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -429,6 +429,7 @@ class RVVIntrinsic {
429429
bool hasBuiltinAlias() const { return HasBuiltinAlias; }
430430
bool hasManualCodegen() const { return !ManualCodegen.empty(); }
431431
bool isMasked() const { return IsMasked; }
432+
llvm::StringRef getOverloadedName() const { return OverloadedName; }
432433
llvm::StringRef getIRName() const { return IRName; }
433434
llvm::StringRef getManualCodegen() const { return ManualCodegen; }
434435
PolicyScheme getPolicyScheme() const { return Scheme; }

clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21751,13 +21751,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2175121751
}
2175221752

2175321753
Intrinsic::ID ID = Intrinsic::not_intrinsic;
21754-
unsigned NF = 1;
2175521754
// The 0th bit simulates the `vta` of RVV
2175621755
// The 1st bit simulates the `vma` of RVV
2175721756
constexpr unsigned RVV_VTA = 0x1;
2175821757
constexpr unsigned RVV_VMA = 0x2;
2175921758
int PolicyAttrs = 0;
2176021759
bool IsMasked = false;
21760+
// This is used by segment load/store to determine it's llvm type.
21761+
unsigned SegInstSEW = 8;
2176121762

2176221763
// Required for overloaded intrinsics.
2176321764
llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;

clang/lib/CodeGen/CodeGenTypes.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -513,14 +513,15 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
513513
{
514514
ASTContext::BuiltinVectorTypeInfo Info =
515515
Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(Ty));
516-
// Tuple types are expressed as aggregregate types of the same scalable
517-
// vector type (e.g. vint32m1x2_t is two vint32m1_t, which is {<vscale x
518-
// 2 x i32>, <vscale x 2 x i32>}).
519516
if (Info.NumVectors != 1) {
520-
llvm::Type *EltTy = llvm::ScalableVectorType::get(
521-
ConvertType(Info.ElementType), Info.EC.getKnownMinValue());
522-
llvm::SmallVector<llvm::Type *, 4> EltTys(Info.NumVectors, EltTy);
523-
return llvm::StructType::get(getLLVMContext(), EltTys);
517+
unsigned I8EltCount =
518+
Info.EC.getKnownMinValue() *
519+
ConvertType(Info.ElementType)->getScalarSizeInBits() / 8;
520+
return llvm::TargetExtType::get(
521+
getLLVMContext(), "riscv_vec_tuple",
522+
llvm::ScalableVectorType::get(
523+
llvm::Type::getInt8Ty(getLLVMContext()), I8EltCount),
524+
Info.NumVectors);
524525
}
525526
return llvm::ScalableVectorType::get(ConvertType(Info.ElementType),
526527
Info.EC.getKnownMinValue());

clang/lib/Support/RISCVVIntrinsicUtils.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1011,7 +1011,7 @@ RVVIntrinsic::RVVIntrinsic(
10111011
(!IsMasked && hasPassthruOperand())) {
10121012
for (auto &I : IntrinsicTypes) {
10131013
if (I >= 0)
1014-
I += NF;
1014+
I += 1;
10151015
}
10161016
}
10171017
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c

Lines changed: 166 additions & 166 deletions
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clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c

Lines changed: 50 additions & 50 deletions
Large diffs are not rendered by default.

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -8,112 +8,112 @@
88

99
#include <riscv_vector.h>
1010

11-
// CHECK-RV64-LABEL: define dso_local { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @test_vloxseg2ei16_v_bf16mf4x2(
11+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(
1212
// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
1313
// CHECK-RV64-NEXT: entry:
14-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @llvm.riscv.vloxseg2.nxv1bf16.nxv1i16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], i64 [[VL]])
15-
// CHECK-RV64-NEXT: ret { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } [[TMP0]]
14+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv2i8_2t.nxv1i16.i64(target("riscv_vec_tuple", <vscale x 2 x i8>, 2) poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], i64 [[VL]], i64 0)
15+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 2 x i8>, 2) [[TMP0]]
1616
//
1717
vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2(const __bf16 *rs1,
1818
vuint16mf4_t rs2, size_t vl) {
1919
return __riscv_vloxseg2ei16_v_bf16mf4x2(rs1, rs2, vl);
2020
}
2121

22-
// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @test_vloxseg2ei16_v_bf16mf2x2(
22+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(
2323
// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
2424
// CHECK-RV64-NEXT: entry:
25-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @llvm.riscv.vloxseg2.nxv2bf16.nxv2i16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], i64 [[VL]])
26-
// CHECK-RV64-NEXT: ret { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } [[TMP0]]
25+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv4i8_2t.nxv2i16.i64(target("riscv_vec_tuple", <vscale x 4 x i8>, 2) poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], i64 [[VL]], i64 0)
26+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 4 x i8>, 2) [[TMP0]]
2727
//
2828
vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2(const __bf16 *rs1,
2929
vuint16mf2_t rs2, size_t vl) {
3030
return __riscv_vloxseg2ei16_v_bf16mf2x2(rs1, rs2, vl);
3131
}
3232

33-
// CHECK-RV64-LABEL: define dso_local { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @test_vloxseg2ei16_v_bf16m1x2(
33+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(
3434
// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
3535
// CHECK-RV64-NEXT: entry:
36-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @llvm.riscv.vloxseg2.nxv4bf16.nxv4i16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], i64 [[VL]])
37-
// CHECK-RV64-NEXT: ret { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } [[TMP0]]
36+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv8i8_2t.nxv4i16.i64(target("riscv_vec_tuple", <vscale x 8 x i8>, 2) poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], i64 [[VL]], i64 0)
37+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 8 x i8>, 2) [[TMP0]]
3838
//
3939
vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2(const __bf16 *rs1, vuint16m1_t rs2,
4040
size_t vl) {
4141
return __riscv_vloxseg2ei16_v_bf16m1x2(rs1, rs2, vl);
4242
}
4343

44-
// CHECK-RV64-LABEL: define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_vloxseg2ei16_v_bf16m2x2(
44+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(
4545
// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 8 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
4646
// CHECK-RV64-NEXT: entry:
47-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.riscv.vloxseg2.nxv8bf16.nxv8i16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], i64 [[VL]])
48-
// CHECK-RV64-NEXT: ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP0]]
47+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv16i8_2t.nxv8i16.i64(target("riscv_vec_tuple", <vscale x 16 x i8>, 2) poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], i64 [[VL]], i64 0)
48+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 16 x i8>, 2) [[TMP0]]
4949
//
5050
vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2(const __bf16 *rs1, vuint16m2_t rs2,
5151
size_t vl) {
5252
return __riscv_vloxseg2ei16_v_bf16m2x2(rs1, rs2, vl);
5353
}
5454

55-
// CHECK-RV64-LABEL: define dso_local { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @test_vloxseg2ei16_v_bf16m4x2(
55+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(
5656
// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 16 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
5757
// CHECK-RV64-NEXT: entry:
58-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @llvm.riscv.vloxseg2.nxv16bf16.nxv16i16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], i64 [[VL]])
59-
// CHECK-RV64-NEXT: ret { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } [[TMP0]]
58+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv32i8_2t.nxv16i16.i64(target("riscv_vec_tuple", <vscale x 32 x i8>, 2) poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], i64 [[VL]], i64 0)
59+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 32 x i8>, 2) [[TMP0]]
6060
//
6161
vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2(const __bf16 *rs1, vuint16m4_t rs2,
6262
size_t vl) {
6363
return __riscv_vloxseg2ei16_v_bf16m4x2(rs1, rs2, vl);
6464
}
6565

66-
// CHECK-RV64-LABEL: define dso_local { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @test_vloxseg2ei16_v_bf16mf4x2_m(
66+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(
6767
// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
6868
// CHECK-RV64-NEXT: entry:
69-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
70-
// CHECK-RV64-NEXT: ret { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } [[TMP0]]
69+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv2i8_2t.nxv1i16.nxv1i1.i64(target("riscv_vec_tuple", <vscale x 2 x i8>, 2) poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
70+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 2 x i8>, 2) [[TMP0]]
7171
//
7272
vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_m(vbool64_t vm,
7373
const __bf16 *rs1,
7474
vuint16mf4_t rs2, size_t vl) {
7575
return __riscv_vloxseg2ei16_v_bf16mf4x2_m(vm, rs1, rs2, vl);
7676
}
7777

78-
// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @test_vloxseg2ei16_v_bf16mf2x2_m(
78+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(
7979
// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
8080
// CHECK-RV64-NEXT: entry:
81-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
82-
// CHECK-RV64-NEXT: ret { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } [[TMP0]]
81+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv4i8_2t.nxv2i16.nxv2i1.i64(target("riscv_vec_tuple", <vscale x 4 x i8>, 2) poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
82+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 4 x i8>, 2) [[TMP0]]
8383
//
8484
vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_m(vbool32_t vm,
8585
const __bf16 *rs1,
8686
vuint16mf2_t rs2, size_t vl) {
8787
return __riscv_vloxseg2ei16_v_bf16mf2x2_m(vm, rs1, rs2, vl);
8888
}
8989

90-
// CHECK-RV64-LABEL: define dso_local { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @test_vloxseg2ei16_v_bf16m1x2_m(
90+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(
9191
// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
9292
// CHECK-RV64-NEXT: entry:
93-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
94-
// CHECK-RV64-NEXT: ret { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } [[TMP0]]
93+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv8i8_2t.nxv4i16.nxv4i1.i64(target("riscv_vec_tuple", <vscale x 8 x i8>, 2) poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
94+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 8 x i8>, 2) [[TMP0]]
9595
//
9696
vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1,
9797
vuint16m1_t rs2, size_t vl) {
9898
return __riscv_vloxseg2ei16_v_bf16m1x2_m(vm, rs1, rs2, vl);
9999
}
100100

101-
// CHECK-RV64-LABEL: define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_vloxseg2ei16_v_bf16m2x2_m(
101+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_m(
102102
// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
103103
// CHECK-RV64-NEXT: entry:
104-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
105-
// CHECK-RV64-NEXT: ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP0]]
104+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv16i8_2t.nxv8i16.nxv8i1.i64(target("riscv_vec_tuple", <vscale x 16 x i8>, 2) poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
105+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 16 x i8>, 2) [[TMP0]]
106106
//
107107
vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1,
108108
vuint16m2_t rs2, size_t vl) {
109109
return __riscv_vloxseg2ei16_v_bf16m2x2_m(vm, rs1, rs2, vl);
110110
}
111111

112-
// CHECK-RV64-LABEL: define dso_local { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @test_vloxseg2ei16_v_bf16m4x2_m(
112+
// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_m(
113113
// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
114114
// CHECK-RV64-NEXT: entry:
115-
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
116-
// CHECK-RV64-NEXT: ret { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } [[TMP0]]
115+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv32i8_2t.nxv16i16.nxv16i1.i64(target("riscv_vec_tuple", <vscale x 32 x i8>, 2) poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
116+
// CHECK-RV64-NEXT: ret target("riscv_vec_tuple", <vscale x 32 x i8>, 2) [[TMP0]]
117117
//
118118
vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1,
119119
vuint16m4_t rs2, size_t vl) {

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