[llvm][RISCV] Support RISCV vector tuple type in llvm IR

Currently we have built-in C types for RISCV vector tuple type, e.g.
`vint32m1x2_t`, however it's is represented as structure of scalable
vector types, i.e. `{<vscale x 2 x i32>, <vscale x 2 x i32>}`. It loses
the information for num_fields(NF) as struct is flattened during selection
DAG, thus it makes it not possible to handle inline assembly of vector
tuple type, it also makes the calling convention of vector tuple types
handing not strait forward and hard to realize the allocation code, i.e.
`RVVArgDispatcher`.

This patch supports RISCV vector tuple types represented as `TargetExtType`
which contains both `LMUL` and `NF`(num_fields) information and keep it all the
way down to `selectionDAG` to match the corresponding `MVT`(support in the
following patch). The llvm IR for the example above is then represented
as `target("riscv_vec_tuple", <vscale x 8 x i8>, 2)` in which the first
type parameter is the equivalent size scalable vecotr of i8 element type,
the following integer parameter is the `NF` of the tuple.

The new RISCV specific vector insert/extract intrinsics are also added
as `llvm.riscv.vector.insert` and `llvm.riscv.vector.extract` to handle
tuple type subvector inserttoin/extraction since the generic ones only
operates on `VectorType` but not `TargetExtType`.

There are total of 32 llvm types added for each `VREGS * NF <= 8`, where
`VREGS` is the vector registers needed for each `LMUL` and `NF` is num_fields.
The name of types are:
```
target("riscv_vec_tuple", <vscale x 1 x i8>, 2)  // LMUL = mf8, NF = 2
target("riscv_vec_tuple", <vscale x 1 x i8>, 3)  // LMUL = mf8, NF = 3
target("riscv_vec_tuple", <vscale x 1 x i8>, 4)  // LMUL = mf8, NF = 4
target("riscv_vec_tuple", <vscale x 1 x i8>, 5)  // LMUL = mf8, NF = 5
target("riscv_vec_tuple", <vscale x 1 x i8>, 6)  // LMUL = mf8, NF = 6
target("riscv_vec_tuple", <vscale x 1 x i8>, 7)  // LMUL = mf8, NF = 7
target("riscv_vec_tuple", <vscale x 1 x i8>, 8)  // LMUL = mf8, NF = 8
target("riscv_vec_tuple", <vscale x 2 x i8>, 2)  // LMUL = mf4, NF = 2
target("riscv_vec_tuple", <vscale x 2 x i8>, 3)  // LMUL = mf4, NF = 3
target("riscv_vec_tuple", <vscale x 2 x i8>, 4)  // LMUL = mf4, NF = 4
target("riscv_vec_tuple", <vscale x 2 x i8>, 5)  // LMUL = mf4, NF = 5
target("riscv_vec_tuple", <vscale x 2 x i8>, 6)  // LMUL = mf4, NF = 6
target("riscv_vec_tuple", <vscale x 2 x i8>, 7)  // LMUL = mf4, NF = 7
target("riscv_vec_tuple", <vscale x 2 x i8>, 8)  // LMUL = mf4, NF = 8
target("riscv_vec_tuple", <vscale x 4 x i8>, 2)  // LMUL = mf2, NF = 2
target("riscv_vec_tuple", <vscale x 4 x i8>, 3)  // LMUL = mf2, NF = 3
target("riscv_vec_tuple", <vscale x 4 x i8>, 4)  // LMUL = mf2, NF = 4
target("riscv_vec_tuple", <vscale x 4 x i8>, 5)  // LMUL = mf2, NF = 5
target("riscv_vec_tuple", <vscale x 4 x i8>, 6)  // LMUL = mf2, NF = 6
target("riscv_vec_tuple", <vscale x 4 x i8>, 7)  // LMUL = mf2, NF = 7
target("riscv_vec_tuple", <vscale x 4 x i8>, 8)  // LMUL = mf2, NF = 8
target("riscv_vec_tuple", <vscale x 8 x i8>, 2)  // LMUL = m1, NF = 2
target("riscv_vec_tuple", <vscale x 8 x i8>, 3)  // LMUL = m1, NF = 3
target("riscv_vec_tuple", <vscale x 8 x i8>, 4)  // LMUL = m1, NF = 4
target("riscv_vec_tuple", <vscale x 8 x i8>, 5)  // LMUL = m1, NF = 5
target("riscv_vec_tuple", <vscale x 8 x i8>, 6)  // LMUL = m1, NF = 6
target("riscv_vec_tuple", <vscale x 8 x i8>, 7)  // LMUL = m1, NF = 7
target("riscv_vec_tuple", <vscale x 8 x i8>, 8)  // LMUL = m1, NF = 8
target("riscv_vec_tuple", <vscale x 16 x i8>, 2) // LMUL = m2, NF = 2
target("riscv_vec_tuple", <vscale x 16 x i8>, 3) // LMUL = m2, NF = 3
target("riscv_vec_tuple", <vscale x 16 x i8>, 4) // LMUL = m2, NF = 4
target("riscv_vec_tuple", <vscale x 32 x i8>, 2) // LMUL = m4, NF = 2
```

Author: 4vtomat

clang/include/clang/Basic/riscv_vector.td

@@ -429,6 +429,7 @@ class RVVIntrinsic {
   bool hasBuiltinAlias() const { return HasBuiltinAlias; }
   bool hasManualCodegen() const { return !ManualCodegen.empty(); }
   bool isMasked() const { return IsMasked; }
+  llvm::StringRef getOverloadedName() const { return OverloadedName; }
   llvm::StringRef getIRName() const { return IRName; }
   llvm::StringRef getManualCodegen() const { return ManualCodegen; }
   PolicyScheme getPolicyScheme() const { return Scheme; }

clang/include/clang/Support/RISCVVIntrinsicUtils.h

@@ -21751,13 +21751,14 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
   }
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
-  unsigned NF = 1;
   // The 0th bit simulates the `vta` of RVV
   // The 1st bit simulates the `vma` of RVV
   constexpr unsigned RVV_VTA = 0x1;
   constexpr unsigned RVV_VMA = 0x2;
   int PolicyAttrs = 0;
   bool IsMasked = false;
+  // This is used by segment load/store to determine it's llvm type.
+  unsigned SegInstSEW = 8;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;

clang/lib/CodeGen/CGBuiltin.cpp

@@ -513,14 +513,15 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
       {
         ASTContext::BuiltinVectorTypeInfo Info =
             Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(Ty));
-        // Tuple types are expressed as aggregregate types of the same scalable
-        // vector type (e.g. vint32m1x2_t is two vint32m1_t, which is {<vscale x
-        // 2 x i32>, <vscale x 2 x i32>}).
         if (Info.NumVectors != 1) {
-          llvm::Type *EltTy = llvm::ScalableVectorType::get(
-              ConvertType(Info.ElementType), Info.EC.getKnownMinValue());
-          llvm::SmallVector<llvm::Type *, 4> EltTys(Info.NumVectors, EltTy);
-          return llvm::StructType::get(getLLVMContext(), EltTys);
+          unsigned I8EltCount =
+              Info.EC.getKnownMinValue() *
+              ConvertType(Info.ElementType)->getScalarSizeInBits() / 8;
+          return llvm::TargetExtType::get(
+              getLLVMContext(), "riscv_vec_tuple",
+              llvm::ScalableVectorType::get(
+                  llvm::Type::getInt8Ty(getLLVMContext()), I8EltCount),
+              Info.NumVectors);
         }
         return llvm::ScalableVectorType::get(ConvertType(Info.ElementType),
                                              Info.EC.getKnownMinValue());

clang/lib/CodeGen/CodeGenTypes.cpp

@@ -1011,7 +1011,7 @@ RVVIntrinsic::RVVIntrinsic(
       (!IsMasked && hasPassthruOperand())) {
     for (auto &I : IntrinsicTypes) {
       if (I >= 0)
-        I += NF;
+        I += 1;
     }
   }
 }

clang/lib/Support/RISCVVIntrinsicUtils.cpp

@@ -8,112 +8,112 @@
 
 #include <riscv_vector.h>
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @test_vloxseg2ei16_v_bf16mf4x2(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2(
 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @llvm.riscv.vloxseg2.nxv1bf16.nxv1i16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], i64 [[VL]])
-// CHECK-RV64-NEXT:    ret { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv2i8_2t.nxv1i16.i64(target("riscv_vec_tuple", <vscale x 2 x i8>, 2) poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 2 x i8>, 2) [[TMP0]]
 //
 vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2(const __bf16 *rs1,
                                                vuint16mf4_t rs2, size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16mf4x2(rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @test_vloxseg2ei16_v_bf16mf2x2(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2(
 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @llvm.riscv.vloxseg2.nxv2bf16.nxv2i16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], i64 [[VL]])
-// CHECK-RV64-NEXT:    ret { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv4i8_2t.nxv2i16.i64(target("riscv_vec_tuple", <vscale x 4 x i8>, 2) poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 4 x i8>, 2) [[TMP0]]
 //
 vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2(const __bf16 *rs1,
                                                vuint16mf2_t rs2, size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16mf2x2(rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @test_vloxseg2ei16_v_bf16m1x2(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2(
 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @llvm.riscv.vloxseg2.nxv4bf16.nxv4i16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], i64 [[VL]])
-// CHECK-RV64-NEXT:    ret { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv8i8_2t.nxv4i16.i64(target("riscv_vec_tuple", <vscale x 8 x i8>, 2) poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 8 x i8>, 2) [[TMP0]]
 //
 vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2(const __bf16 *rs1, vuint16m1_t rs2,
                                              size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16m1x2(rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_vloxseg2ei16_v_bf16m2x2(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2(
 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 8 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.riscv.vloxseg2.nxv8bf16.nxv8i16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], i64 [[VL]])
-// CHECK-RV64-NEXT:    ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv16i8_2t.nxv8i16.i64(target("riscv_vec_tuple", <vscale x 16 x i8>, 2) poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 16 x i8>, 2) [[TMP0]]
 //
 vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2(const __bf16 *rs1, vuint16m2_t rs2,
                                              size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16m2x2(rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @test_vloxseg2ei16_v_bf16m4x2(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2(
 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 16 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @llvm.riscv.vloxseg2.nxv16bf16.nxv16i16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], i64 [[VL]])
-// CHECK-RV64-NEXT:    ret { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv_vec_tuple_nxv32i8_2t.nxv16i16.i64(target("riscv_vec_tuple", <vscale x 32 x i8>, 2) poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 32 x i8>, 2) [[TMP0]]
 //
 vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2(const __bf16 *rs1, vuint16m4_t rs2,
                                              size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16m4x2(rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @test_vloxseg2ei16_v_bf16mf4x2_m(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @test_vloxseg2ei16_v_bf16mf4x2_m(
 // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT:    ret { <vscale x 1 x bfloat>, <vscale x 1 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv2i8_2t.nxv1i16.nxv1i1.i64(target("riscv_vec_tuple", <vscale x 2 x i8>, 2) poison, ptr [[RS1]], <vscale x 1 x i16> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 2 x i8>, 2) [[TMP0]]
 //
 vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_m(vbool64_t vm,
                                                  const __bf16 *rs1,
                                                  vuint16mf4_t rs2, size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16mf4x2_m(vm, rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @test_vloxseg2ei16_v_bf16mf2x2_m(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @test_vloxseg2ei16_v_bf16mf2x2_m(
 // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT:    ret { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv4i8_2t.nxv2i16.nxv2i1.i64(target("riscv_vec_tuple", <vscale x 4 x i8>, 2) poison, ptr [[RS1]], <vscale x 2 x i16> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 4 x i8>, 2) [[TMP0]]
 //
 vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_m(vbool32_t vm,
                                                  const __bf16 *rs1,
                                                  vuint16mf2_t rs2, size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16mf2x2_m(vm, rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @test_vloxseg2ei16_v_bf16m1x2_m(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @test_vloxseg2ei16_v_bf16m1x2_m(
 // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT:    ret { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv8i8_2t.nxv4i16.nxv4i1.i64(target("riscv_vec_tuple", <vscale x 8 x i8>, 2) poison, ptr [[RS1]], <vscale x 4 x i16> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 8 x i8>, 2) [[TMP0]]
 //
 vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1,
                                                vuint16m1_t rs2, size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16m1x2_m(vm, rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @test_vloxseg2ei16_v_bf16m2x2_m(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @test_vloxseg2ei16_v_bf16m2x2_m(
 // CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT:    ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 16 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv16i8_2t.nxv8i16.nxv8i1.i64(target("riscv_vec_tuple", <vscale x 16 x i8>, 2) poison, ptr [[RS1]], <vscale x 8 x i16> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 16 x i8>, 2) [[TMP0]]
 //
 vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1,
                                                vuint16m2_t rs2, size_t vl) {
   return __riscv_vloxseg2ei16_v_bf16m2x2_m(vm, rs1, rs2, vl);
 }
 
-// CHECK-RV64-LABEL: define dso_local { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @test_vloxseg2ei16_v_bf16m4x2_m(
+// CHECK-RV64-LABEL: define dso_local target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @test_vloxseg2ei16_v_bf16m4x2_m(
 // CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i16> [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT:    ret { <vscale x 16 x bfloat>, <vscale x 16 x bfloat> } [[TMP0]]
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call target("riscv_vec_tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv_vec_tuple_nxv32i8_2t.nxv16i16.nxv16i1.i64(target("riscv_vec_tuple", <vscale x 32 x i8>, 2) poison, ptr [[RS1]], <vscale x 16 x i16> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3, i64 0)
+// CHECK-RV64-NEXT:    ret target("riscv_vec_tuple", <vscale x 32 x i8>, 2) [[TMP0]]
 //
 vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1,
                                                vuint16m4_t rs2, size_t vl) {