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[ELF] Pass Ctx & to Arch/
1 parent 6d03a69 commit b3e0bd3

15 files changed

+52
-47
lines changed

‎lld/ELF/AArch64ErrataFix.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -372,7 +372,7 @@ static uint64_t scanCortexA53Errata843419(InputSection *isec, uint64_t &off,
372372

373373
class elf::Patch843419Section final : public SyntheticSection {
374374
public:
375-
Patch843419Section(InputSection *p, uint64_t off);
375+
Patch843419Section(Ctx &, InputSection *p, uint64_t off);
376376

377377
void writeTo(Ctx &, uint8_t *buf) override;
378378

@@ -392,7 +392,7 @@ class elf::Patch843419Section final : public SyntheticSection {
392392
Symbol *patchSym;
393393
};
394394

395-
Patch843419Section::Patch843419Section(InputSection *p, uint64_t off)
395+
Patch843419Section::Patch843419Section(Ctx &ctx, InputSection *p, uint64_t off)
396396
: SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 4,
397397
".text.patch"),
398398
patchee(p), patcheeOffset(off) {
@@ -529,7 +529,7 @@ void AArch64Err843419Patcher::insertPatches(
529529
// instruction that we need to patch at patcheeOffset from the start of
530530
// InputSection isec, create a Patch843419 Section and add it to the
531531
// Patches that we need to insert.
532-
static void implementPatch(uint64_t adrpAddr, uint64_t patcheeOffset,
532+
static void implementPatch(Ctx &ctx, uint64_t adrpAddr, uint64_t patcheeOffset,
533533
InputSection *isec,
534534
std::vector<Patch843419Section *> &patches) {
535535
// There may be a relocation at the same offset that we are patching. There
@@ -556,7 +556,7 @@ static void implementPatch(uint64_t adrpAddr, uint64_t patcheeOffset,
556556
log("detected cortex-a53-843419 erratum sequence starting at " +
557557
utohexstr(adrpAddr) + " in unpatched output.");
558558

559-
auto *ps = make<Patch843419Section>(isec, patcheeOffset);
559+
auto *ps = make<Patch843419Section>(ctx, isec, patcheeOffset);
560560
patches.push_back(ps);
561561

562562
auto makeRelToPatch = [](uint64_t offset, Symbol *patchSym) {
@@ -599,7 +599,7 @@ AArch64Err843419Patcher::patchInputSectionDescription(
599599
uint64_t startAddr = isec->getVA(off);
600600
if (uint64_t patcheeOffset =
601601
scanCortexA53Errata843419(isec, off, limit))
602-
implementPatch(startAddr, patcheeOffset, isec, patches);
602+
implementPatch(ctx, startAddr, patcheeOffset, isec, patches);
603603
}
604604
if (dataSym == mapSyms.end())
605605
break;

‎lld/ELF/ARMErrataFix.cpp

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,8 @@ uint64_t Patch657417Section::getBranchAddr() const {
151151

152152
// Given a branch instruction instr at sourceAddr work out its destination
153153
// address. This is only used when the branch instruction has no relocation.
154-
static uint64_t getThumbDestAddr(uint64_t sourceAddr, uint32_t instr) {
154+
static uint64_t getThumbDestAddr(Ctx &ctx, uint64_t sourceAddr,
155+
uint32_t instr) {
155156
uint8_t buf[4];
156157
write16le(buf, instr >> 16);
157158
write16le(buf + 2, instr & 0x0000ffff);
@@ -191,7 +192,7 @@ void Patch657417Section::writeTo(Ctx &ctx, uint8_t *buf) {
191192
// Get the destination offset from the addend in the branch instruction.
192193
// We cannot use the instruction in the patchee section as this will have
193194
// been altered to point to us!
194-
uint64_t s = getThumbDestAddr(getBranchAddr(), instr);
195+
uint64_t s = getThumbDestAddr(ctx, getBranchAddr(), instr);
195196
// A BLX changes the state of the branch in the patch to Arm state, which
196197
// has a PC Bias of 8, whereas in all other cases the branch is in Thumb
197198
// state with a PC Bias of 4.
@@ -204,8 +205,9 @@ void Patch657417Section::writeTo(Ctx &ctx, uint8_t *buf) {
204205
// Given a branch instruction spanning two 4KiB regions, at offset off from the
205206
// start of isec, return true if the destination of the branch is within the
206207
// first of the two 4Kib regions.
207-
static bool branchDestInFirstRegion(const InputSection *isec, uint64_t off,
208-
uint32_t instr, const Relocation *r) {
208+
static bool branchDestInFirstRegion(Ctx &ctx, const InputSection *isec,
209+
uint64_t off, uint32_t instr,
210+
const Relocation *r) {
209211
uint64_t sourceAddr = isec->getVA(0) + off;
210212
assert((sourceAddr & 0xfff) == 0xffe);
211213
uint64_t destAddr;
@@ -219,15 +221,15 @@ static bool branchDestInFirstRegion(const InputSection *isec, uint64_t off,
219221
} else {
220222
// If there is no relocation, we must have an intra-section branch
221223
// We must extract the offset from the addend manually.
222-
destAddr = getThumbDestAddr(sourceAddr, instr);
224+
destAddr = getThumbDestAddr(ctx, sourceAddr, instr);
223225
}
224226

225227
return (destAddr & 0xfffff000) == (sourceAddr & 0xfffff000);
226228
}
227229

228230
// Return true if a branch can reach a patch section placed after isec.
229231
// The Bcc.w instruction has a range of 1 MiB, all others have 16 MiB.
230-
static bool patchInRange(const InputSection *isec, uint64_t off,
232+
static bool patchInRange(Ctx &ctx, const InputSection *isec, uint64_t off,
231233
uint32_t instr) {
232234

233235
// We need the branch at source to reach a patch section placed immediately
@@ -289,8 +291,8 @@ static ScanResult scanCortexA8Errata657417(InputSection *isec, uint64_t &off,
289291
});
290292
if (relIt != isec->relocs().end())
291293
scanRes.rel = &(*relIt);
292-
if (branchDestInFirstRegion(isec, branchOff, instr2, scanRes.rel)) {
293-
if (patchInRange(isec, branchOff, instr2)) {
294+
if (branchDestInFirstRegion(ctx, isec, branchOff, instr2, scanRes.rel)) {
295+
if (patchInRange(ctx, isec, branchOff, instr2)) {
294296
scanRes.off = branchOff;
295297
scanRes.instr = instr2;
296298
} else {

‎lld/ELF/ARMErrataFix.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,15 @@
1414
#include <vector>
1515

1616
namespace lld::elf {
17-
17+
struct Ctx;
1818
class Defined;
1919
class InputSection;
2020
class InputSectionDescription;
2121
class Patch657417Section;
2222

2323
class ARMErr657417Patcher {
2424
public:
25+
ARMErr657417Patcher(Ctx &ctx) : ctx(ctx) {}
2526
// Return true if Patches have been added to the OutputSections.
2627
bool createFixes();
2728

@@ -34,6 +35,7 @@ class ARMErr657417Patcher {
3435

3536
void init();
3637

38+
Ctx &ctx;
3739
// A cache of the mapping symbols defined by the InputSection sorted in order
3840
// of ascending value with redundant symbols removed. These describe
3941
// the ranges of code and data in an executable InputSection.

‎lld/ELF/Arch/ARM.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -230,14 +230,14 @@ static void writePltHeaderLong(Ctx &ctx, uint8_t *buf) {
230230

231231
// True if we should use Thumb PLTs, which currently require Thumb2, and are
232232
// only used if the target does not have the ARM ISA.
233-
static bool useThumbPLTs() {
233+
static bool useThumbPLTs(Ctx &ctx) {
234234
return ctx.arg.armHasThumb2ISA && !ctx.arg.armHasArmISA;
235235
}
236236

237237
// The default PLT header requires the .got.plt to be within 128 Mb of the
238238
// .plt in the positive direction.
239239
void ARM::writePltHeader(uint8_t *buf) const {
240-
if (useThumbPLTs()) {
240+
if (useThumbPLTs(ctx)) {
241241
// The instruction sequence for thumb:
242242
//
243243
// 0: b500 push {lr}
@@ -295,7 +295,7 @@ void ARM::writePltHeader(uint8_t *buf) const {
295295
}
296296

297297
void ARM::addPltHeaderSymbols(InputSection &isec) const {
298-
if (useThumbPLTs()) {
298+
if (useThumbPLTs(ctx)) {
299299
addSyntheticLocal("$t", STT_NOTYPE, 0, 0, isec);
300300
addSyntheticLocal("$d", STT_NOTYPE, 12, 0, isec);
301301
} else {
@@ -320,8 +320,7 @@ static void writePltLong(uint8_t *buf, uint64_t gotPltEntryAddr,
320320
// .plt in the positive direction.
321321
void ARM::writePlt(uint8_t *buf, const Symbol &sym,
322322
uint64_t pltEntryAddr) const {
323-
324-
if (!useThumbPLTs()) {
323+
if (!useThumbPLTs(ctx)) {
325324
uint64_t offset = sym.getGotPltVA() - pltEntryAddr - 8;
326325

327326
// The PLT entry is similar to the example given in Appendix A of ELF for
@@ -373,7 +372,7 @@ void ARM::writePlt(uint8_t *buf, const Symbol &sym,
373372
}
374373

375374
void ARM::addPltSymbols(InputSection &isec, uint64_t off) const {
376-
if (useThumbPLTs()) {
375+
if (useThumbPLTs(ctx)) {
377376
addSyntheticLocal("$t", STT_NOTYPE, off, 0, isec);
378377
} else {
379378
addSyntheticLocal("$a", STT_NOTYPE, off, 0, isec);
@@ -399,7 +398,7 @@ bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
399398
case R_ARM_JUMP24:
400399
// Source is ARM, all PLT entries are ARM so no interworking required.
401400
// Otherwise we need to interwork if STT_FUNC Symbol has bit 0 set (Thumb).
402-
assert(!useThumbPLTs() &&
401+
assert(!useThumbPLTs(ctx) &&
403402
"If the source is ARM, we should not need Thumb PLTs");
404403
if (s.isFunc() && expr == R_PC && (s.getVA() & 1))
405404
return true;
@@ -413,7 +412,7 @@ bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
413412
case R_ARM_THM_JUMP24:
414413
// Source is Thumb, when all PLT entries are ARM interworking is required.
415414
// Otherwise we need to interwork if STT_FUNC Symbol has bit 0 clear (ARM).
416-
if ((expr == R_PLT_PC && !useThumbPLTs()) ||
415+
if ((expr == R_PLT_PC && !useThumbPLTs(ctx)) ||
417416
(s.isFunc() && (s.getVA() & 1) == 0))
418417
return true;
419418
[[fallthrough]];
@@ -683,7 +682,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
683682
// PLT entries are always ARM state so we know we need to interwork.
684683
assert(rel.sym); // R_ARM_THM_CALL is always reached via relocate().
685684
bool bit0Thumb = val & 1;
686-
bool useThumb = bit0Thumb || useThumbPLTs();
685+
bool useThumb = bit0Thumb || useThumbPLTs(ctx);
687686
bool isBlx = (read16(loc + 2) & 0x1000) == 0;
688687
// lld 10.0 and before always used bit0Thumb when deciding to write a BLX
689688
// even when type not STT_FUNC.
@@ -1330,7 +1329,8 @@ class elf::ArmCmseSGVeneer {
13301329
ArmCmseSGSection::ArmCmseSGSection(Ctx &ctx)
13311330
: SyntheticSection(llvm::ELF::SHF_ALLOC | llvm::ELF::SHF_EXECINSTR,
13321331
llvm::ELF::SHT_PROGBITS,
1333-
/*alignment=*/32, ".gnu.sgstubs") {
1332+
/*alignment=*/32, ".gnu.sgstubs"),
1333+
ctx(ctx) {
13341334
entsize = ACLESESYM_SIZE;
13351335
// The range of addresses used in the CMSE import library should be fixed.
13361336
for (auto &[_, sym] : ctx.symtab->cmseImportLib) {

‎lld/ELF/Arch/Mips.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,7 @@ template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const {
206206
template <class ELFT>
207207
void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const {
208208
uint64_t va = ctx.in.plt->getVA();
209-
if (isMicroMips())
209+
if (isMicroMips(ctx))
210210
va |= 1;
211211
write32(buf, va);
212212
}
@@ -256,7 +256,7 @@ static void writeMicroRelocation16(uint8_t *loc, uint64_t v, uint8_t bitsSize,
256256
}
257257

258258
template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const {
259-
if (isMicroMips()) {
259+
if (isMicroMips(ctx)) {
260260
uint64_t gotPlt = ctx.in.gotPlt->getVA();
261261
uint64_t plt = ctx.in.plt->getVA();
262262
// Overwrite trap instructions written by Writer::writeTrapInstr.
@@ -320,7 +320,7 @@ template <class ELFT>
320320
void MIPS<ELFT>::writePlt(uint8_t *buf, const Symbol &sym,
321321
uint64_t pltEntryAddr) const {
322322
uint64_t gotPltEntryAddr = sym.getGotPltVA();
323-
if (isMicroMips()) {
323+
if (isMicroMips(ctx)) {
324324
// Overwrite trap instructions written by Writer::writeTrapInstr.
325325
memset(buf, 0, pltEntrySize);
326326

‎lld/ELF/Arch/MipsArchTree.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212

1313
#include "InputFiles.h"
1414
#include "SymbolTable.h"
15+
#include "Target.h"
1516
#include "Writer.h"
1617

1718
#include "lld/Common/ErrorHandler.h"
@@ -381,7 +382,7 @@ bool elf::isMipsN32Abi(Ctx &ctx, const InputFile &f) {
381382
}
382383
}
383384

384-
bool elf::isMicroMips() { return ctx.arg.eflags & EF_MIPS_MICROMIPS; }
385+
bool elf::isMicroMips(Ctx &ctx) { return ctx.arg.eflags & EF_MIPS_MICROMIPS; }
385386

386387
bool elf::isMipsR6(Ctx &ctx) {
387388
uint32_t arch = ctx.arg.eflags & EF_MIPS_ARCH;

‎lld/ELF/Driver.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@ bool LinkerDriver::tryAddFatLTOFile(MemoryBufferRef mb, StringRef archiveName,
273273
if (errorToBool(fatLTOData.takeError()))
274274
return false;
275275
files.push_back(
276-
make<BitcodeFile>(*fatLTOData, archiveName, offsetInArchive, lazy));
276+
make<BitcodeFile>(ctx, *fatLTOData, archiveName, offsetInArchive, lazy));
277277
return true;
278278
}
279279

@@ -300,7 +300,8 @@ void LinkerDriver::addFile(StringRef path, bool withLOption) {
300300
if (inWholeArchive) {
301301
for (const std::pair<MemoryBufferRef, uint64_t> &p : members) {
302302
if (isBitcode(p.first))
303-
files.push_back(make<BitcodeFile>(p.first, path, p.second, false));
303+
files.push_back(
304+
make<BitcodeFile>(ctx, p.first, path, p.second, false));
304305
else if (!tryAddFatLTOFile(p.first, path, p.second, false))
305306
files.push_back(createObjFile(p.first, path));
306307
}
@@ -329,7 +330,7 @@ void LinkerDriver::addFile(StringRef path, bool withLOption) {
329330
if (!tryAddFatLTOFile(p.first, path, p.second, true))
330331
files.push_back(createObjFile(p.first, path, true));
331332
} else if (magic == file_magic::bitcode)
332-
files.push_back(make<BitcodeFile>(p.first, path, p.second, true));
333+
files.push_back(make<BitcodeFile>(ctx, p.first, path, p.second, true));
333334
else
334335
warn(path + ": archive member '" + p.first.getBufferIdentifier() +
335336
"' is neither ET_REL nor LLVM bitcode");
@@ -357,7 +358,7 @@ void LinkerDriver::addFile(StringRef path, bool withLOption) {
357358
return;
358359
}
359360
case file_magic::bitcode:
360-
files.push_back(make<BitcodeFile>(mbref, "", 0, inLib));
361+
files.push_back(make<BitcodeFile>(ctx, mbref, "", 0, inLib));
361362
break;
362363
case file_magic::elf_relocatable:
363364
if (!tryAddFatLTOFile(mbref, "", 0, inLib))

‎lld/ELF/InputFiles.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1698,7 +1698,7 @@ static uint8_t getOsAbi(const Triple &t) {
16981698
}
16991699
}
17001700

1701-
BitcodeFile::BitcodeFile(MemoryBufferRef mb, StringRef archiveName,
1701+
BitcodeFile::BitcodeFile(Ctx &ctx, MemoryBufferRef mb, StringRef archiveName,
17021702
uint64_t offsetInArchive, bool lazy)
17031703
: InputFile(BitcodeKind, mb) {
17041704
this->archiveName = archiveName;

‎lld/ELF/InputFiles.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ template <class ELFT> class ObjFile : public ELFFileBase {
326326

327327
class BitcodeFile : public InputFile {
328328
public:
329-
BitcodeFile(MemoryBufferRef m, StringRef archiveName,
329+
BitcodeFile(Ctx &, MemoryBufferRef m, StringRef archiveName,
330330
uint64_t offsetInArchive, bool lazy);
331331
static bool classof(const InputFile *f) { return f->kind() == BitcodeKind; }
332332
void parse();

‎lld/ELF/Symbols.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ static uint64_t getSymVA(const Symbol &sym, int64_t addend) {
109109
// a symbol value as-is (.dynamic section, `Elf_Ehdr::e_entry`
110110
// field etc) do the same trick as compiler uses to mark microMIPS
111111
// for CPU - set the less-significant bit.
112-
if (ctx.arg.emachine == EM_MIPS && isMicroMips() &&
112+
if (ctx.arg.emachine == EM_MIPS && isMicroMips(ctx) &&
113113
((sym.stOther & STO_MIPS_MICROMIPS) || sym.hasFlag(NEEDS_COPY)))
114114
va |= 1;
115115

@@ -177,7 +177,7 @@ uint64_t Symbol::getPltVA() const {
177177
// While linking microMIPS code PLT code are always microMIPS
178178
// code. Set the less-significant bit to track that fact.
179179
// See detailed comment in the `getSymVA` function.
180-
if (ctx.arg.emachine == EM_MIPS && isMicroMips())
180+
if (ctx.arg.emachine == EM_MIPS && isMicroMips(ctx))
181181
outVA |= 1;
182182
return outVA;
183183
}

‎lld/ELF/SyntheticSections.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2302,7 +2302,7 @@ void SymbolTableSection<ELFT>::writeTo(Ctx &ctx, uint8_t *buf) {
23022302
Symbol *sym = ent.sym;
23032303
if (sym->isInPlt() && sym->hasFlag(NEEDS_COPY))
23042304
eSym->st_other |= STO_MIPS_PLT;
2305-
if (isMicroMips()) {
2305+
if (isMicroMips(ctx)) {
23062306
// We already set the less-significant bit for symbols
23072307
// marked by the `STO_MIPS_MICROMIPS` flag and for microMIPS PLT
23082308
// records. That allows us to distinguish such symbols in

‎lld/ELF/SyntheticSections.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1322,6 +1322,7 @@ class ArmCmseSGSection final : public SyntheticSection {
13221322
uint64_t impLibMaxAddr = 0;
13231323

13241324
private:
1325+
Ctx &ctx;
13251326
SmallVector<std::pair<Symbol *, Symbol *>, 0> entries;
13261327
SmallVector<ArmCmseSGVeneer *, 0> sgVeneers;
13271328
uint64_t newEntries = 0;

‎lld/ELF/Target.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,13 @@ static inline std::string getErrorLocation(const uint8_t *loc) {
210210

211211
void processArmCmseSymbols(Ctx &);
212212

213+
template <class ELFT> uint32_t calcMipsEFlags(Ctx &);
214+
uint8_t getMipsFpAbiFlag(uint8_t oldFlag, uint8_t newFlag,
215+
llvm::StringRef fileName);
216+
bool isMipsN32Abi(Ctx &, const InputFile &f);
217+
bool isMicroMips(Ctx &);
218+
bool isMipsR6(Ctx &);
219+
213220
void writePPC32GlinkSection(Ctx &, uint8_t *buf, size_t numEntries);
214221

215222
unsigned getPPCDFormOp(unsigned secondaryOp);

‎lld/ELF/Writer.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1439,7 +1439,7 @@ template <class ELFT> void Writer<ELFT>::finalizeAddressDependentContent() {
14391439
llvm::TimeTraceScope timeScope("Finalize address dependent content");
14401440
ThunkCreator tc(ctx);
14411441
AArch64Err843419Patcher a64p(ctx);
1442-
ARMErr657417Patcher a32p;
1442+
ARMErr657417Patcher a32p(ctx);
14431443
ctx.script->assignAddresses();
14441444

14451445
// .ARM.exidx and SHF_LINK_ORDER do not require precise addresses, but they

‎lld/ELF/Writer.h

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -48,15 +48,6 @@ void addReservedSymbols(Ctx &ctx);
4848
bool includeInSymtab(const Symbol &b);
4949
unsigned getSectionRank(Ctx &, OutputSection &osec);
5050

51-
template <class ELFT> uint32_t calcMipsEFlags(Ctx &);
52-
53-
uint8_t getMipsFpAbiFlag(uint8_t oldFlag, uint8_t newFlag,
54-
llvm::StringRef fileName);
55-
56-
bool isMipsN32Abi(Ctx &, const InputFile &f);
57-
bool isMicroMips();
58-
bool isMipsR6(Ctx &);
59-
6051
} // namespace lld::elf
6152

6253
#endif

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