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davemgreendavemgreen
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Attempt to use LocationSize
1 parent bfb6753 commit bb7072c

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+276
-284
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -647,15 +647,15 @@ bool GIMatchTableExecutor::executeMatchTable(
647647

648648
unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
649649
if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
650-
MMO->getSizeInBits() != Size) {
650+
MMO->getSizeInBits().getValue() != Size) {
651651
if (handleReject() == RejectAndGiveUp)
652652
return false;
653653
} else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
654-
MMO->getSizeInBits() >= Size) {
654+
MMO->getSizeInBits().getValue() >= Size) {
655655
if (handleReject() == RejectAndGiveUp)
656656
return false;
657657
} else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
658-
MMO->getSizeInBits() <= Size)
658+
MMO->getSizeInBits().getValue() <= Size)
659659
if (handleReject() == RejectAndGiveUp)
660660
return false;
661661

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,9 @@ class GMemOperation : public GenericMachineInstr {
5454
bool isUnordered() const { return getMMO().isUnordered(); }
5555

5656
/// Returns the size in bytes of the memory access.
57-
uint64_t getMemSize() const { return getMMO().getSize(); }
57+
LocationSize getMemSize() const { return getMMO().getSize(); }
5858
/// Returns the size in bits of the memory access.
59-
uint64_t getMemSizeInBits() const { return getMMO().getSizeInBits(); }
59+
LocationSize getMemSizeInBits() const { return getMMO().getSizeInBits(); }
6060

6161
static bool classof(const MachineInstr *MI) {
6262
return GenericMachineInstr::classof(MI) && MI->hasOneMemOperand();

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 41 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1026,25 +1026,37 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10261026
/// MachineMemOperands are owned by the MachineFunction and need not be
10271027
/// explicitly deallocated.
10281028
MachineMemOperand *getMachineMemOperand(
1029-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s,
1029+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy,
10301030
Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
10311031
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10321032
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
10331033
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
1034-
10351034
MachineMemOperand *getMachineMemOperand(
1036-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
1035+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, LocationSize TS,
10371036
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
10381037
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10391038
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
10401039
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
1041-
10421040
MachineMemOperand *getMachineMemOperand(
1043-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy,
1044-
Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
1041+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, uint64_t TS,
1042+
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
10451043
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10461044
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
1047-
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
1045+
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic) {
1046+
return getMachineMemOperand(PtrInfo, F, LocationSize::precise(TS),
1047+
BaseAlignment, AAInfo, Ranges, SSID, Ordering,
1048+
FailureOrdering);
1049+
}
1050+
MachineMemOperand *getMachineMemOperand(
1051+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
1052+
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
1053+
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
1054+
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
1055+
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic) {
1056+
return getMachineMemOperand(PtrInfo, F, LocationSize::precise(TS),
1057+
BaseAlignment, AAInfo, Ranges, SSID, Ordering,
1058+
FailureOrdering);
1059+
}
10481060

10491061
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
10501062
/// an existing one, adjusting by an offset and using the given size.
@@ -1053,18 +1065,21 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10531065
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10541066
int64_t Offset, LLT Ty);
10551067
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1056-
int64_t Offset, uint64_t Size) {
1068+
int64_t Offset, LocationSize TS) {
10571069
return getMachineMemOperand(
1058-
MMO, Offset, Size == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * Size));
1070+
MMO, Offset,
1071+
!TS.hasValue() ? LLT()
1072+
: TS.isScalable()
1073+
? LLT::scalable_vector(1, 8 * TS.getValue().getKnownMinValue())
1074+
: LLT::scalar(8 * TS.getValue().getKnownMinValue()));
10591075
}
1060-
10611076
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1062-
int64_t Offset, TypeSize TS) {
1063-
return getMachineMemOperand(
1064-
MMO, Offset,
1065-
TS.getKnownMinValue() == ~UINT64_C(0) ? LLT()
1066-
: TS.isScalable() ? LLT::scalable_vector(1, 8 * TS.getKnownMinValue())
1067-
: LLT::scalar(8 * TS.getKnownMinValue()));
1077+
int64_t Offset, uint64_t Size) {
1078+
return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
1079+
}
1080+
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1081+
int64_t Offset, TypeSize Size) {
1082+
return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
10681083
}
10691084

10701085
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
@@ -1073,13 +1088,20 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10731088
/// explicitly deallocated.
10741089
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10751090
const MachinePointerInfo &PtrInfo,
1076-
uint64_t Size);
1091+
LocationSize TS);
10771092
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10781093
const MachinePointerInfo &PtrInfo,
1079-
TypeSize TS);
1094+
LLT Ty);
10801095
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10811096
const MachinePointerInfo &PtrInfo,
1082-
LLT Ty);
1097+
uint64_t Size) {
1098+
return getMachineMemOperand(MMO, PtrInfo, LocationSize::precise(Size));
1099+
}
1100+
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1101+
const MachinePointerInfo &PtrInfo,
1102+
TypeSize Size) {
1103+
return getMachineMemOperand(MMO, PtrInfo, LocationSize::precise(Size));
1104+
}
10831105

10841106
/// Allocate a new MachineMemOperand by copying an existing one,
10851107
/// replacing only AliasAnalysis information. MachineMemOperands are owned

‎llvm/include/llvm/CodeGen/MachineMemOperand.h

Lines changed: 10 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717

1818
#include "llvm/ADT/BitmaskEnum.h"
1919
#include "llvm/ADT/PointerUnion.h"
20+
#include "llvm/Analysis/MemoryLocation.h"
2021
#include "llvm/CodeGen/PseudoSourceValue.h"
2122
#include "llvm/CodeGenTypes/LowLevelType.h"
2223
#include "llvm/IR/DerivedTypes.h"
@@ -186,13 +187,7 @@ class MachineMemOperand {
186187
/// and atomic ordering requirements must also be specified. For cmpxchg
187188
/// atomic operations the atomic ordering requirements when store does not
188189
/// occur must also be specified.
189-
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
190-
Align a, const AAMDNodes &AAInfo = AAMDNodes(),
191-
const MDNode *Ranges = nullptr,
192-
SyncScope::ID SSID = SyncScope::System,
193-
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
194-
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
195-
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, TypeSize TS,
190+
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LocationSize TS,
196191
Align a, const AAMDNodes &AAInfo = AAMDNodes(),
197192
const MDNode *Ranges = nullptr,
198193
SyncScope::ID SSID = SyncScope::System,
@@ -241,15 +236,17 @@ class MachineMemOperand {
241236
LLT getMemoryType() const { return MemoryType; }
242237

243238
/// Return the size in bytes of the memory reference.
244-
TypeSize getSize() const {
245-
return MemoryType.isValid() ? MemoryType.getSizeInBytes()
246-
: TypeSize::getFixed(~UINT64_C(0));
239+
LocationSize getSize() const {
240+
return MemoryType.isValid()
241+
? LocationSize::precise(MemoryType.getSizeInBytes())
242+
: LocationSize::beforeOrAfterPointer();
247243
}
248244

249245
/// Return the size in bits of the memory reference.
250-
TypeSize getSizeInBits() const {
251-
return MemoryType.isValid() ? MemoryType.getSizeInBits()
252-
: TypeSize::getFixed(~UINT64_C(0));
246+
LocationSize getSizeInBits() const {
247+
return MemoryType.isValid()
248+
? LocationSize::precise(MemoryType.getSizeInBits())
249+
: LocationSize::beforeOrAfterPointer();
253250
}
254251

255252
LLT getType() const {

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1299,15 +1299,15 @@ class SelectionDAG {
12991299
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
13001300
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
13011301
MachineMemOperand::MOStore,
1302-
uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes());
1302+
LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes());
13031303

13041304
inline SDValue getMemIntrinsicNode(
13051305
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
13061306
EVT MemVT, MachinePointerInfo PtrInfo,
13071307
MaybeAlign Alignment = std::nullopt,
13081308
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
13091309
MachineMemOperand::MOStore,
1310-
uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
1310+
LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
13111311
// Ensure that codegen never sees alignment 0
13121312
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
13131313
Alignment.value_or(getEVTAlign(MemVT)), Flags,

‎llvm/lib/CodeGen/DFAPacketizer.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -252,12 +252,13 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
252252
bool VLIWPacketizerList::alias(const MachineMemOperand &Op1,
253253
const MachineMemOperand &Op2,
254254
bool UseTBAA) const {
255-
if (!Op1.getValue() || !Op2.getValue())
255+
if (!Op1.getValue() || !Op2.getValue() || !Op1.getSize().hasValue() ||
256+
!Op2.getSize().hasValue())
256257
return true;
257258

258259
int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset());
259-
int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset;
260-
int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset;
260+
int64_t Overlapa = Op1.getSize().getValue() + Op1.getOffset() - MinOffset;
261+
int64_t Overlapb = Op2.getSize().getValue() + Op2.getOffset() - MinOffset;
261262

262263
AliasResult AAResult =
263264
AA->alias(MemoryLocation(Op1.getValue(), Overlapa,

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -770,12 +770,12 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
770770
LLT RegTy = MRI.getType(LoadReg);
771771
Register PtrReg = LoadMI->getPointerReg();
772772
unsigned RegSize = RegTy.getSizeInBits();
773-
uint64_t LoadSizeBits = LoadMI->getMemSizeInBits();
773+
LocationSize LoadSizeBits = LoadMI->getMemSizeInBits();
774774
unsigned MaskSizeBits = MaskVal.countr_one();
775775

776776
// The mask may not be larger than the in-memory type, as it might cover sign
777777
// extended bits
778-
if (MaskSizeBits > LoadSizeBits)
778+
if (MaskSizeBits > LoadSizeBits.getValue())
779779
return false;
780780

781781
// If the mask covers the whole destination register, there's nothing to
@@ -795,7 +795,8 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
795795
// still adjust the opcode to indicate the high bit behavior.
796796
if (LoadMI->isSimple())
797797
MemDesc.MemoryTy = LLT::scalar(MaskSizeBits);
798-
else if (LoadSizeBits > MaskSizeBits || LoadSizeBits == RegSize)
798+
else if (LoadSizeBits.getValue() > MaskSizeBits ||
799+
LoadSizeBits.getValue() == RegSize)
799800
return false;
800801

801802
// TODO: Could check if it's legal with the reduced or original memory size.
@@ -860,7 +861,8 @@ bool CombinerHelper::matchSextTruncSextLoad(MachineInstr &MI) {
860861
if (auto *LoadMI = getOpcodeDef<GSExtLoad>(LoadUser, MRI)) {
861862
// If truncating more than the original extended value, abort.
862863
auto LoadSizeBits = LoadMI->getMemSizeInBits();
863-
if (TruncSrc && MRI.getType(TruncSrc).getSizeInBits() < LoadSizeBits)
864+
if (TruncSrc &&
865+
MRI.getType(TruncSrc).getSizeInBits() < LoadSizeBits.getValue())
864866
return false;
865867
if (LoadSizeBits == SizeInBits)
866868
return true;
@@ -891,7 +893,7 @@ bool CombinerHelper::matchSextInRegOfLoad(
891893
if (!LoadDef || !MRI.hasOneNonDBGUse(DstReg))
892894
return false;
893895

894-
uint64_t MemBits = LoadDef->getMemSizeInBits();
896+
uint64_t MemBits = LoadDef->getMemSizeInBits().getValue();
895897

896898
// If the sign extend extends from a narrower width than the load's width,
897899
// then we can narrow the load width when we combine to a G_SEXTLOAD.

‎llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -415,7 +415,8 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
415415
if (DstTy.isVector())
416416
break;
417417
// Everything above the retrieved bits is zero
418-
Known.Zero.setBitsFrom((*MI.memoperands_begin())->getSizeInBits());
418+
Known.Zero.setBitsFrom(
419+
(*MI.memoperands_begin())->getSizeInBits().getValue());
419420
break;
420421
}
421422
case TargetOpcode::G_ASHR: {
@@ -666,7 +667,7 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
666667

667668
// e.g. i16->i32 = '17' bits known.
668669
const MachineMemOperand *MMO = *MI.memoperands_begin();
669-
return TyBits - MMO->getSizeInBits() + 1;
670+
return TyBits - MMO->getSizeInBits().getValue() + 1;
670671
}
671672
case TargetOpcode::G_ZEXTLOAD: {
672673
// FIXME: We need an in-memory type representation.
@@ -675,7 +676,7 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
675676

676677
// e.g. i16->i32 = '16' bits known.
677678
const MachineMemOperand *MMO = *MI.memoperands_begin();
678-
return TyBits - MMO->getSizeInBits();
679+
return TyBits - MMO->getSizeInBits().getValue();
679680
}
680681
case TargetOpcode::G_TRUNC: {
681682
Register Src = MI.getOperand(1).getReg();

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1317,7 +1317,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
13171317
if (DstTy.isVector())
13181318
return UnableToLegalize;
13191319

1320-
if (8 * LoadMI.getMemSize() != DstTy.getSizeInBits()) {
1320+
if (8 * LoadMI.getMemSize().getValue() != DstTy.getSizeInBits()) {
13211321
Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
13221322
MIRBuilder.buildLoad(TmpReg, LoadMI.getPointerReg(), LoadMI.getMMO());
13231323
MIRBuilder.buildAnyExt(DstReg, TmpReg);
@@ -1335,7 +1335,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
13351335

13361336
Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
13371337
auto &MMO = LoadMI.getMMO();
1338-
unsigned MemSize = MMO.getSizeInBits();
1338+
unsigned MemSize = MMO.getSizeInBits().getValue();
13391339

13401340
if (MemSize == NarrowSize) {
13411341
MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
@@ -1368,7 +1368,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
13681368
if (SrcTy.isVector() && LeftoverBits != 0)
13691369
return UnableToLegalize;
13701370

1371-
if (8 * StoreMI.getMemSize() != SrcTy.getSizeInBits()) {
1371+
if (8 * StoreMI.getMemSize().getValue() != SrcTy.getSizeInBits()) {
13721372
Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
13731373
MIRBuilder.buildTrunc(TmpReg, SrcReg);
13741374
MIRBuilder.buildStore(TmpReg, StoreMI.getPointerReg(), StoreMI.getMMO());
@@ -4449,7 +4449,7 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
44494449
LLT ValTy = MRI.getType(ValReg);
44504450

44514451
// FIXME: Do we need a distinct NarrowMemory legalize action?
4452-
if (ValTy.getSizeInBits() != 8 * LdStMI.getMemSize()) {
4452+
if (ValTy.getSizeInBits() != 8 * LdStMI.getMemSize().getValue()) {
44534453
LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n");
44544454
return UnableToLegalize;
44554455
}

‎llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -117,12 +117,8 @@ bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1,
117117
if (!BasePtr0.BaseReg.isValid() || !BasePtr1.BaseReg.isValid())
118118
return false;
119119

120-
LocationSize Size1 = LdSt1->getMemSize() != MemoryLocation::UnknownSize
121-
? LdSt1->getMemSize()
122-
: LocationSize::beforeOrAfterPointer();
123-
LocationSize Size2 = LdSt2->getMemSize() != MemoryLocation::UnknownSize
124-
? LdSt2->getMemSize()
125-
: LocationSize::beforeOrAfterPointer();
120+
LocationSize Size1 = LdSt1->getMemSize();
121+
LocationSize Size2 = LdSt2->getMemSize();
126122

127123
int64_t PtrDiff;
128124
if (BasePtr0.BaseReg == BasePtr1.BaseReg) {
@@ -132,14 +128,14 @@ bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1,
132128
// vector objects on the stack.
133129
// BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the
134130
// following situations arise:
135-
if (PtrDiff >= 0 && Size1.hasValue()) {
131+
if (PtrDiff >= 0 && Size1.hasValue() && !Size1.isScalable()) {
136132
// [----BasePtr0----]
137133
// [---BasePtr1--]
138134
// ========PtrDiff========>
139135
IsAlias = !((int64_t)Size1.getValue() <= PtrDiff);
140136
return true;
141137
}
142-
if (PtrDiff < 0 && Size2.hasValue()) {
138+
if (PtrDiff < 0 && Size2.hasValue() && !Size2.isScalable()) {
143139
// [----BasePtr0----]
144140
// [---BasePtr1--]
145141
// =====(-PtrDiff)====>
@@ -214,9 +210,9 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
214210
Offset = 0;
215211
}
216212

217-
TypeSize Size = LS->getMMO().getMemoryType().getSizeInBytes();
218-
return {LS->isVolatile(), LS->isAtomic(), BaseReg,
219-
Offset /*base offset*/, LocationSize::precise(Size), &LS->getMMO()};
213+
LocationSize Size = LS->getMMO().getSize();
214+
return {LS->isVolatile(), LS->isAtomic(), BaseReg,
215+
Offset /*base offset*/, Size, &LS->getMMO()};
220216
}
221217
// FIXME: support recognizing lifetime instructions.
222218
// Default.
@@ -254,12 +250,12 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
254250

255251
// If NumBytes is scalable and offset is not 0, conservatively return may
256252
// alias
257-
if ((MUC0.NumBytes.isScalable() && (MUC0.Offset != 0)) ||
258-
(MUC1.NumBytes.isScalable() && (MUC1.Offset != 0)))
253+
if ((MUC0.NumBytes.isScalable() && MUC0.Offset != 0) ||
254+
(MUC1.NumBytes.isScalable() && MUC1.Offset != 0))
259255
return true;
260256

261257
const bool BothNotScalable =
262-
!(MUC0.NumBytes.isScalable() || MUC1.NumBytes.isScalable());
258+
!MUC0.NumBytes.isScalable() && !MUC1.NumBytes.isScalable();
263259

264260
// Try to prove that there is aliasing, or that there is no aliasing. Either
265261
// way, we can return now. If nothing can be proved, proceed with more tests.
@@ -527,7 +523,7 @@ bool LoadStoreOpt::addStoreToCandidate(GStore &StoreMI,
527523
return false;
528524

529525
// Don't allow truncating stores for now.
530-
if (StoreMI.getMemSizeInBits() != ValueTy.getSizeInBits())
526+
if (StoreMI.getMemSizeInBits().getValue() != ValueTy.getSizeInBits())
531527
return false;
532528

533529
// Avoid adding volatile or ordered stores to the candidate. We already have a

‎llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1356,7 +1356,7 @@ InstrRefBasedLDV::findLocationForMemOperand(const MachineInstr &MI) {
13561356
// from the stack at some point. Happily the memory operand will tell us
13571357
// the size written to the stack.
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auto *MemOperand = *MI.memoperands_begin();
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unsigned SizeInBits = MemOperand->getSizeInBits();
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unsigned SizeInBits = MemOperand->getSizeInBits().getValue();
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// Find that position in the stack indexes we're tracking.
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auto IdxIt = MTracker->StackSlotIdxes.find({SizeInBits, 0});

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