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[RISCV] Make A implies Zaamo and Zalrsc (#116907)
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.
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‎clang/test/CodeGen/RISCV/riscv-func-attr-target.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() {
6666
}
6767

6868
//.
69-
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa" }
70-
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
71-
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" }
72-
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
69+
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" }
70+
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
71+
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }
72+
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
7373
// Make sure we append negative features if we override the arch
74-
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
74+
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
7575
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
76-
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" }
76+
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" }
7777
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
78-
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
79-
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
80-
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
81-
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }
78+
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
79+
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
80+
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
81+
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }

‎lld/test/ELF/lto/riscv-attributes.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@
1010
; CHECK: BuildAttributes {
1111
; CHECK-NEXT: FormatVersion: 0x41
1212
; CHECK-NEXT: Section 1 {
13-
; CHECK-NEXT: SectionLength: 79
13+
; CHECK-NEXT: SectionLength: 98
1414
; CHECK-NEXT: Vendor: riscv
1515
; CHECK-NEXT: Tag: Tag_File (0x1)
16-
; CHECK-NEXT: Size: 69
16+
; CHECK-NEXT: Size: 88
1717
; CHECK-NEXT: FileAttributes {
1818
; CHECK-NEXT: Attribute {
1919
; CHECK-NEXT: Tag: 4
@@ -30,7 +30,7 @@
3030
; CHECK-NEXT: Attribute {
3131
; CHECK-NEXT: Tag: 5
3232
; CHECK-NEXT: TagName: arch
33-
; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zbb1p0{{$}}
33+
; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zbb1p0{{$}}
3434
; CHECK-NEXT: }
3535
; CHECK-NEXT: }
3636
; CHECK-NEXT: }

‎lld/test/ELF/riscv-attributes.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -104,20 +104,20 @@
104104
# UNKNOWN22: warning: unknown22a.o:(.riscv.attributes): invalid tag 0x16 at offset 0x10
105105

106106
# HDR: Name Type Address Off Size ES Flg Lk Inf Al
107-
# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 000047 00 0 0 1{{$}}
107+
# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 00005a 00 0 0 1{{$}}
108108

109109
# HDR: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
110110
# HDR: LOAD 0x000000 0x0000000000010000 0x0000000000010000 0x000158 0x000158 R 0x1000
111111
# HDR-NEXT: GNU_STACK 0x000000 0x0000000000000000 0x0000000000000000 0x000000 0x000000 RW 0
112-
# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x000047 0x000047 R 0x1{{$}}
112+
# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x00005a 0x00005a R 0x1{{$}}
113113

114114
# CHECK: BuildAttributes {
115115
# CHECK-NEXT: FormatVersion: 0x41
116116
# CHECK-NEXT: Section 1 {
117-
# CHECK-NEXT: SectionLength: 70
117+
# CHECK-NEXT: SectionLength: 89
118118
# CHECK-NEXT: Vendor: riscv
119119
# CHECK-NEXT: Tag: Tag_File (0x1)
120-
# CHECK-NEXT: Size: 60
120+
# CHECK-NEXT: Size: 79
121121
# CHECK-NEXT: FileAttributes {
122122
# CHECK-NEXT: Attribute {
123123
# CHECK-NEXT: Tag: 4
@@ -128,7 +128,7 @@
128128
# CHECK-NEXT: Attribute {
129129
# CHECK-NEXT: Tag: 5
130130
# CHECK-NEXT: TagName: arch
131-
# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0{{$}}
131+
# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0{{$}}
132132
# CHECK-NEXT: }
133133
# CHECK-NEXT: }
134134
# CHECK-NEXT: }
@@ -137,10 +137,10 @@
137137
# CHECK2: BuildAttributes {
138138
# CHECK2-NEXT: FormatVersion: 0x41
139139
# CHECK2-NEXT: Section 1 {
140-
# CHECK2-NEXT: SectionLength: 113
140+
# CHECK2-NEXT: SectionLength: 132
141141
# CHECK2-NEXT: Vendor: riscv
142142
# CHECK2-NEXT: Tag: Tag_File (0x1)
143-
# CHECK2-NEXT: Size: 103
143+
# CHECK2-NEXT: Size: 122
144144
# CHECK2-NEXT: FileAttributes {
145145
# CHECK2-NEXT: Attribute {
146146
# CHECK2-NEXT: Tag: 4
@@ -167,7 +167,7 @@
167167
# CHECK2-NEXT: Attribute {
168168
# CHECK2-NEXT: Tag: 5
169169
# CHECK2-NEXT: TagName: arch
170-
# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
170+
# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
171171
# CHECK2-NEXT: }
172172
# CHECK2-NEXT: }
173173
# CHECK2-NEXT: }

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -203,9 +203,26 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
203203

204204
// Atomic Extensions
205205

206+
def FeatureStdExtZaamo
207+
: RISCVExtension<"zaamo", 1, 0,
208+
"'Zaamo' (Atomic Memory Operations)">;
209+
def HasStdExtZaamo
210+
: Predicate<"Subtarget->hasStdExtZaamo()">,
211+
AssemblerPredicate<(any_of FeatureStdExtZaamo),
212+
"'Zaamo' (Atomic Memory Operations)">;
213+
214+
def FeatureStdExtZalrsc
215+
: RISCVExtension<"zalrsc", 1, 0,
216+
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
217+
def HasStdExtZalrsc
218+
: Predicate<"Subtarget->hasStdExtZalrsc()">,
219+
AssemblerPredicate<(any_of FeatureStdExtZalrsc),
220+
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
221+
206222
def FeatureStdExtA
207223
: RISCVExtension<"a", 2, 1,
208-
"'A' (Atomic Instructions)">,
224+
"'A' (Atomic Instructions)",
225+
[FeatureStdExtZaamo, FeatureStdExtZalrsc]>,
209226
RISCVExtensionBitmask<0, 0>;
210227
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
211228
AssemblerPredicate<(all_of FeatureStdExtA),
@@ -226,15 +243,6 @@ def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
226243
def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
227244
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
228245

229-
def FeatureStdExtZaamo
230-
: RISCVExtension<"zaamo", 1, 0,
231-
"'Zaamo' (Atomic Memory Operations)">;
232-
def HasStdExtAOrZaamo
233-
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
234-
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
235-
"'A' (Atomic Instructions) or "
236-
"'Zaamo' (Atomic Memory Operations)">;
237-
238246
def FeatureStdExtZabha
239247
: RISCVExtension<"zabha", 1, 0,
240248
"'Zabha' (Byte and Halfword Atomic Memory Operations)",
@@ -260,15 +268,6 @@ def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
260268
AssemblerPredicate<(all_of FeatureStdExtZalasr),
261269
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
262270

263-
def FeatureStdExtZalrsc
264-
: RISCVExtension<"zalrsc", 1, 0,
265-
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
266-
def HasStdExtAOrZalrsc
267-
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
268-
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
269-
"'A' (Atomic Instructions) or "
270-
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
271-
272271
def FeatureStdExtZama16b
273272
: RISCVExtension<"zama16b", 1, 0,
274273
"'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoA.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -60,13 +60,13 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
6060
// Instructions
6161
//===----------------------------------------------------------------------===//
6262

63-
let Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1 in {
63+
let Predicates = [HasStdExtZalrsc], IsSignExtendingOpW = 1 in {
6464
defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
6565
defm SC_W : SC_r_aq_rl<0b010, "sc.w">,
6666
Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
67-
} // Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1
67+
} // Predicates = [HasStdExtZalrsc], IsSignExtendingOpW = 1
6868

69-
let Predicates = [HasStdExtAOrZaamo], IsSignExtendingOpW = 1 in {
69+
let Predicates = [HasStdExtZaamo], IsSignExtendingOpW = 1 in {
7070
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
7171
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
7272
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
@@ -85,15 +85,15 @@ defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
8585
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
8686
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
8787
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
88-
} // Predicates = [HasStdExtAOrZaamo], IsSignExtendingOpW = 1
88+
} // Predicates = [HasStdExtZaamo], IsSignExtendingOpW = 1
8989

90-
let Predicates = [HasStdExtAOrZalrsc, IsRV64] in {
90+
let Predicates = [HasStdExtZalrsc, IsRV64] in {
9191
defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>;
9292
defm SC_D : SC_r_aq_rl<0b011, "sc.d">,
9393
Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>;
94-
} // Predicates = [HasStdExtAOrZalrsc, IsRV64]
94+
} // Predicates = [HasStdExtZalrsc, IsRV64]
9595

96-
let Predicates = [HasStdExtAOrZaamo, IsRV64] in {
96+
let Predicates = [HasStdExtZaamo, IsRV64] in {
9797
defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">,
9898
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
9999
defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">,
@@ -112,7 +112,7 @@ defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">,
112112
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
113113
defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
114114
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
115-
} // Predicates = [HasStdExtAOrZaamo, IsRV64]
115+
} // Predicates = [HasStdExtZaamo, IsRV64]
116116

117117
//===----------------------------------------------------------------------===//
118118
// Pseudo-instructions and codegen patterns

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@
306306
; RV32M: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
307307
; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
308308
; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
309-
; RV32A: .attribute 5, "rv32i2p1_a2p1"
309+
; RV32A: .attribute 5, "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
310310
; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
311311
; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
312312
; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
@@ -446,7 +446,7 @@
446446
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
447447
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
448448
; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
449-
; RV64A: .attribute 5, "rv64i2p1_a2p1"
449+
; RV64A: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalrsc1p0"
450450
; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
451451
; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
452452
; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
@@ -590,14 +590,14 @@
590590

591591
; RVI20U32: .attribute 5, "rv32i2p1"
592592
; RVI20U64: .attribute 5, "rv64i2p1"
593-
; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0"
594-
; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
595-
; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
596-
; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
597-
; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0"
598-
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
599-
; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
600-
; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
593+
; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0"
594+
; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
595+
; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
596+
; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
597+
; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0"
598+
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
599+
; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
600+
; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
601601
; RVM23U32: .attribute 5, "rv32i2p1_m2p0_b1p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
602602

603603
define i32 @addi(i32 %a) {

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