Skip to content

Commit fe118f5

Browse files
committed
rebasing
1 parent ab49ccd commit fe118f5

File tree

3 files changed

+10
-13
lines changed

3 files changed

+10
-13
lines changed

llvm/lib/Target/X86/X86FastISel.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3542,7 +3542,9 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
35423542

35433543
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(CallOpc));
35443544
if (NeedLoad)
3545-
MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0);
3545+
MIB.addReg(Is64Bit ? static_cast<unsigned>(X86::RIP) : 0U)
3546+
.addImm(1)
3547+
.addReg(0);
35463548
if (Symbol)
35473549
MIB.addSym(Symbol, OpFlags);
35483550
else

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29975,14 +29975,9 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
2997529975
MVT::getVectorVT(NarrowScalarVT, WideNumElts), dl, AmtWideElts);
2997629976
AmtWide = DAG.getZExtOrTrunc(AmtWide, dl, WideVT);
2997729977
// Perform the actual shift.
29978-
<<<<<<< HEAD
29979-
unsigned LogicalOpc = Opc == ISD::SRA ? ISD::SRL : Opc;
29980-
SDValue ShiftedR = DAG.getNode(LogicalOpc, dl, WideVT, RWide, AmtWide);
29981-
=======
2998229978
unsigned LogicalOpc =
2998329979
Opc == ISD::SRA ? static_cast<unsigned>(ISD::SRL) : Opc;
29984-
SDValue ShiftedR = DAG.getNode(LogicalOpc, dl, VT16, R16, Amt16);
29985-
>>>>>>> ae2283c2c014 (static_cast)
29980+
SDValue ShiftedR = DAG.getNode(LogicalOpc, dl, WideVT, RWide, AmtWide);
2998629981
// Now we need to construct a mask which will "drop" bits that get
2998729982
// shifted past the LSB/MSB. For a logical shift left, it will look
2998829983
// like:

mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -840,13 +840,13 @@ enum VectorMemoryAccessKind { ScalarBroadcast, Contiguous, Gather };
840840
/// TODO: Statically shaped loops + vector masking
841841
static uint64_t getTrailingNonUnitLoopDimIdx(LinalgOp linalgOp) {
842842
SmallVector<int64_t> loopRanges = linalgOp.getStaticLoopRanges();
843-
assert(linalgOp.hasDynamicShape() ||
844-
llvm::count_if(loopRanges, [](int64_t dim) { return dim != 1; }) ==
845-
1 &&
846-
"For statically shaped Linalg Ops, only one "
847-
"non-unit loop dim is expected");
843+
assert(
844+
(linalgOp.hasDynamicShape() ||
845+
llvm::count_if(loopRanges, [](int64_t dim) { return dim != 1; }) == 1) &&
846+
"For statically shaped Linalg Ops, only one "
847+
"non-unit loop dim is expected");
848848

849-
size_t idx = loopRanges.size() - 1;
849+
ssize_t idx = loopRanges.size() - 1;
850850
for (; idx >= 0; idx--)
851851
if (loopRanges[idx] != 1)
852852
break;

0 commit comments

Comments
 (0)