[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (#132704)

Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6
processor.

i6400 and i6500 share same instruction latencies.

CPU has following pipelines
  - Two ALUs
  - Multiply and Divide unit (MDU)
  - Branch Unit (CTU)
  - Load/Store Unit (LSU)
  - Short Floating-point Unit and
  - Long Floating-point Unit
 
Latency information is available at:
https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf

Author: mgoudar

llvm/lib/Target/Mips/Mips.td

@@ -224,6 +224,7 @@ include "MipsRegisterBanks.td"
 include "MipsCombine.td"
 
 // Avoid forward declaration issues.
+include "MipsScheduleI6400.td"
 include "MipsScheduleP5600.td"
 include "MipsScheduleGeneric.td"
 
@@ -271,8 +272,8 @@ def : Proc<"mips64r6", [FeatureMips64r6]>;
 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
-def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
-def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
+def : ProcessorModel<"i6400", MipsI6400Model, [ImplI6400]>;
+def : ProcessorModel<"i6500", MipsI6400Model, [ImplI6500]>;
 
 def MipsAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;